adc.map.qmsg

基于北京革新公司出品的EDA实验工具箱的数模转换程序。该程序将输入的5V信号从01至FF量化并通过2位数码管进行显示。量化精度为0.1v。编译环境为quartusll.5.1版本。fpga芯片为EP1

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 30 11:30:56 2008 " "Info: Processing started: Wed Apr 30 11:30:56 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adc -c adc " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc -c adc" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adc.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adc-adc8is_arch " "Info: Found design unit 1: adc-adc8is_arch" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adc " "Info: Found entity 1: adc" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adc " "Info: Elaborating entity \"adc\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clkcount adc.vhd(29) " "Warning (10492): VHDL Process Statement warning at adc.vhd(29): signal \"clkcount\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data adc.vhd(58) " "Warning (10492): VHDL Process Statement warning at adc.vhd(58): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 58 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data adc.vhd(59) " "Warning (10492): VHDL Process Statement warning at adc.vhd(59): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 59 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "adc.vhd(60) " "Info (10425): VHDL Case Statement information at adc.vhd(60): OTHERS choice is never selected" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 60 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "count clkcount\[0\] " "Info: Duplicate register \"count\" merged to single register \"clkcount\[0\]\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|adc\|fsm1 2 " "Info: State machine \"\|adc\|fsm1\" contains 2 states" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 20 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|adc\|sta 4 " "Info: State machine \"\|adc\|sta\" contains 4 states" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 20 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|adc\|fsm1 " "Info: Selected Auto state machine encoding method for state machine \"\|adc\|fsm1\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 20 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|adc\|fsm1 " "Info: Encoding result for state machine \"\|adc\|fsm1\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "1 " "Info: Completed encoding using 1 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sta_4 " "Info: Encoded state bit \"sta_4\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 38 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|sta_2 0 " "Info: State \"\|adc\|sta_2\" uses code string \"0\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 38 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|sta_4 1 " "Info: State \"\|adc\|sta_4\" uses code string \"1\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 38 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 20 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|adc\|sta " "Info: Selected Auto state machine encoding method for state machine \"\|adc\|sta\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 20 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|adc\|sta " "Info: Encoding result for state machine \"\|adc\|sta\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sta.s3 " "Info: Encoded state bit \"sta.s3\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sta.s2 " "Info: Encoded state bit \"sta.s2\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sta.s1 " "Info: Encoded state bit \"sta.s1\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sta.s0 " "Info: Encoded state bit \"sta.s0\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|sta.s0 0000 " "Info: State \"\|adc\|sta.s0\" uses code string \"0000\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|sta.s1 0011 " "Info: State \"\|adc\|sta.s1\" uses code string \"0011\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|sta.s2 0101 " "Info: State \"\|adc\|sta.s2\" uses code string \"0101\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adc\|sta.s3 1001 " "Info: State \"\|adc\|sta.s3\" uses code string \"1001\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 20 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "sta.s3 rd~reg0 " "Info: Duplicate register \"sta.s3\" merged to single register \"rd~reg0\", power-up level changed" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "sta_4 High " "Info: Power-up level of register \"sta_4\" is not specified -- using power-up level of High to minimize register" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 38 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sta_4 data_in VCC " "Warning: Reduced register \"sta_4\" with stuck data_in port to stuck value VCC" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 38 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "sta.s1 wr~reg0 " "Info: Duplicate register \"sta.s1\" merged to single register \"wr~reg0\", power-up level changed" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "s~106 " "Warning: Removed always-enabled tri-state buffer s~106 feeding logic, open-drain buffer, or output pin" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "s~93 " "Warning: Removed always-enabled tri-state buffer s~93 feeding logic, open-drain buffer, or output pin" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "s~80 " "Warning: Removed always-enabled tri-state buffer s~80 feeding logic, open-drain buffer, or output pin" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "s~70 " "Warning: Removed always-enabled tri-state buffer s~70 feeding logic, open-drain buffer, or output pin" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "s~55 " "Warning: Removed always-enabled tri-state buffer s~55 feeding logic, open-drain buffer, or output pin" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "s~42 " "Warning: Removed always-enabled tri-state buffer s~42 feeding logic, open-drain buffer, or output pin" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "s~28 " "Warning: Removed always-enabled tri-state buffer s~28 feeding logic, open-drain buffer, or output pin" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "int " "Warning: No output dependent on input pin \"int\"" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "55 " "Info: Implemented 55 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "33 " "Info: Implemented 33 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 30 11:30:58 2008 " "Info: Processing ended: Wed Apr 30 11:30:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}