adc.tan.qmsg

基于北京革新公司出品的EDA实验工具箱的数模转换程序。该程序将输入的5V信号从01至FF量化并通过2位数码管进行显示。量化精度为0.1v。编译环境为quartusll.5.1版本。fpga芯片为EP1

{ "Info" "ITDB_TH_RESULT" "data\[7\] dati\[7\] clk 1.505 ns register " "Info: th for register \"data\[7\]\" (data pin = \"dati\[7\]\", clock pin = \"clk\") is 1.505 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.171 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { clk } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns clkcount\[3\] 2 REG LC_X11_Y6_N4 14 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.658 ns" { clk clkcount[3] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.333 ns) + CELL(0.711 ns) 8.171 ns data\[7\] 3 REG LC_X34_Y2_N0 2 " "Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N0; Fanout = 2; REG Node = 'data\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "5.044 ns" { clkcount[3] data[7] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.12 % ) " "Info: Total cell delay = 3.115 ns ( 38.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.056 ns ( 61.88 % ) " "Info: Total interconnect delay = 5.056 ns ( 61.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] data[7] } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.681 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns dati\[7\] 1 PIN PIN_121 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; PIN Node = 'dati\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { dati[7] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.097 ns) + CELL(0.115 ns) 6.681 ns data\[7\] 2 REG LC_X34_Y2_N0 2 " "Info: 2: + IC(5.097 ns) + CELL(0.115 ns) = 6.681 ns; Loc. = LC_X34_Y2_N0; Fanout = 2; REG Node = 'data\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "5.212 ns" { dati[7] data[7] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 23.71 % ) " "Info: Total cell delay = 1.584 ns ( 23.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.097 ns ( 76.29 % ) " "Info: Total interconnect delay = 5.097 ns ( 76.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "6.681 ns" { dati[7] data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.681 ns" { dati[7] dati[7]~out0 data[7] } { 0.000ns 0.000ns 5.097ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] data[7] } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "6.681 ns" { dati[7] data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.681 ns" { dati[7] dati[7]~out0 data[7] } { 0.000ns 0.000ns 5.097ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 30 11:31:07 2008 " "Info: Processing ended: Wed Apr 30 11:31:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}