adc.tan.qmsg

基于北京革新公司出品的EDA实验工具箱的数模转换程序。该程序将输入的5V信号从01至FF量化并通过2位数码管进行显示。量化精度为0.1v。编译环境为quartusll.5.1版本。fpga芯片为EP1

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkcount\[3\] " "Info: Detected ripple clock \"clkcount\[3\]\" as buffer" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 16 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkcount\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register rd~reg0 data\[2\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"rd~reg0\" and destination register \"data\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.449 ns + Longest register register " "Info: + Longest register to register delay is 1.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rd~reg0 1 REG LC_X34_Y2_N7 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N7; Fanout = 10; REG Node = 'rd~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { rd~reg0 } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.867 ns) 1.449 ns data\[2\] 2 REG LC_X34_Y2_N5 1 " "Info: 2: + IC(0.582 ns) + CELL(0.867 ns) = 1.449 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'data\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.449 ns" { rd~reg0 data[2] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.867 ns ( 59.83 % ) " "Info: Total cell delay = 0.867 ns ( 59.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.582 ns ( 40.17 % ) " "Info: Total interconnect delay = 0.582 ns ( 40.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.449 ns" { rd~reg0 data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.449 ns" { rd~reg0 data[2] } { 0.000ns 0.582ns } { 0.000ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.171 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { clk } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns clkcount\[3\] 2 REG LC_X11_Y6_N4 14 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.658 ns" { clk clkcount[3] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.333 ns) + CELL(0.711 ns) 8.171 ns data\[2\] 3 REG LC_X34_Y2_N5 1 " "Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'data\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "5.044 ns" { clkcount[3] data[2] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.12 % ) " "Info: Total cell delay = 3.115 ns ( 38.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.056 ns ( 61.88 % ) " "Info: Total interconnect delay = 5.056 ns ( 61.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] data[2] } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.171 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { clk } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns clkcount\[3\] 2 REG LC_X11_Y6_N4 14 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.658 ns" { clk clkcount[3] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.333 ns) + CELL(0.711 ns) 8.171 ns rd~reg0 3 REG LC_X34_Y2_N7 10 " "Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N7; Fanout = 10; REG Node = 'rd~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "5.044 ns" { clkcount[3] rd~reg0 } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.12 % ) " "Info: Total cell delay = 3.115 ns ( 38.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.056 ns ( 61.88 % ) " "Info: Total interconnect delay = 5.056 ns ( 61.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] rd~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] rd~reg0 } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] data[2] } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] rd~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] rd~reg0 } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.449 ns" { rd~reg0 data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.449 ns" { rd~reg0 data[2] } { 0.000ns 0.582ns } { 0.000ns 0.867ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] data[2] } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] rd~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] rd~reg0 } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { data[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { data[2] } {  } {  } } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "data\[0\] dati\[0\] clk -1.128 ns register " "Info: tsu for register \"data\[0\]\" (data pin = \"dati\[0\]\", clock pin = \"clk\") is -1.128 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.006 ns + Longest pin register " "Info: + Longest pin to register delay is 7.006 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns dati\[0\] 1 PIN PIN_114 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_114; Fanout = 1; PIN Node = 'dati\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { dati[0] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.416 ns) + CELL(0.115 ns) 7.006 ns data\[0\] 2 REG LC_X34_Y2_N4 1 " "Info: 2: + IC(5.416 ns) + CELL(0.115 ns) = 7.006 ns; Loc. = LC_X34_Y2_N4; Fanout = 1; REG Node = 'data\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "5.531 ns" { dati[0] data[0] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 22.69 % ) " "Info: Total cell delay = 1.590 ns ( 22.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.416 ns ( 77.31 % ) " "Info: Total interconnect delay = 5.416 ns ( 77.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "7.006 ns" { dati[0] data[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.006 ns" { dati[0] dati[0]~out0 data[0] } { 0.000ns 0.000ns 5.416ns } { 0.000ns 1.475ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.171 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { clk } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns clkcount\[3\] 2 REG LC_X11_Y6_N4 14 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.658 ns" { clk clkcount[3] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.333 ns) + CELL(0.711 ns) 8.171 ns data\[0\] 3 REG LC_X34_Y2_N4 1 " "Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N4; Fanout = 1; REG Node = 'data\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "5.044 ns" { clkcount[3] data[0] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.12 % ) " "Info: Total cell delay = 3.115 ns ( 38.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.056 ns ( 61.88 % ) " "Info: Total interconnect delay = 5.056 ns ( 61.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] data[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] data[0] } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "7.006 ns" { dati[0] data[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.006 ns" { dati[0] dati[0]~out0 data[0] } { 0.000ns 0.000ns 5.416ns } { 0.000ns 1.475ns 0.115ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] data[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] data[0] } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk s\[1\] data\[5\] 17.774 ns register " "Info: tco from clock \"clk\" to destination pin \"s\[1\]\" through register \"data\[5\]\" is 17.774 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.171 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { clk } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns clkcount\[3\] 2 REG LC_X11_Y6_N4 14 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.658 ns" { clk clkcount[3] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.333 ns) + CELL(0.711 ns) 8.171 ns data\[5\] 3 REG LC_X34_Y2_N1 2 " "Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N1; Fanout = 2; REG Node = 'data\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "5.044 ns" { clkcount[3] data[5] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.12 % ) " "Info: Total cell delay = 3.115 ns ( 38.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.056 ns ( 61.88 % ) " "Info: Total interconnect delay = 5.056 ns ( 61.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] data[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] data[5] } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.379 ns + Longest register pin " "Info: + Longest register to pin delay is 9.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data\[5\] 1 REG LC_X34_Y2_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N1; Fanout = 2; REG Node = 'data\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "" { data[5] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.590 ns) 1.120 ns hexd\[1\]~65 2 COMB LC_X34_Y2_N3 9 " "Info: 2: + IC(0.530 ns) + CELL(0.590 ns) = 1.120 ns; Loc. = LC_X34_Y2_N3; Fanout = 9; COMB Node = 'hexd\[1\]~65'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.120 ns" { data[5] hexd[1]~65 } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.104 ns) + CELL(0.590 ns) 4.814 ns s~1365 3 COMB LC_X34_Y19_N9 1 " "Info: 3: + IC(3.104 ns) + CELL(0.590 ns) = 4.814 ns; Loc. = LC_X34_Y19_N9; Fanout = 1; COMB Node = 's~1365'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "3.694 ns" { hexd[1]~65 s~1365 } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.590 ns) 5.826 ns s~1366 4 COMB LC_X34_Y19_N4 1 " "Info: 4: + IC(0.422 ns) + CELL(0.590 ns) = 5.826 ns; Loc. = LC_X34_Y19_N4; Fanout = 1; COMB Node = 's~1366'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "1.012 ns" { s~1365 s~1366 } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.429 ns) + CELL(2.124 ns) 9.379 ns s\[1\] 5 PIN PIN_179 0 " "Info: 5: + IC(1.429 ns) + CELL(2.124 ns) = 9.379 ns; Loc. = PIN_179; Fanout = 0; PIN Node = 's\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "3.553 ns" { s~1366 s[1] } "NODE_NAME" } "" } } { "adc.vhd" "" { Text "E:/竞赛/adc1/adc.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.894 ns ( 41.52 % ) " "Info: Total cell delay = 3.894 ns ( 41.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.485 ns ( 58.48 % ) " "Info: Total interconnect delay = 5.485 ns ( 58.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "9.379 ns" { data[5] hexd[1]~65 s~1365 s~1366 s[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.379 ns" { data[5] hexd[1]~65 s~1365 s~1366 s[1] } { 0.000ns 0.530ns 3.104ns 0.422ns 1.429ns } { 0.000ns 0.590ns 0.590ns 0.590ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "8.171 ns" { clk clkcount[3] data[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.171 ns" { clk clk~out0 clkcount[3] data[5] } { 0.000ns 0.000ns 0.723ns 4.333ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc" "UNKNOWN" "V1" "E:/竞赛/adc1/db/adc.quartus_db" { Floorplan "E:/竞赛/adc1/" "" "9.379 ns" { data[5] hexd[1]~65 s~1365 s~1366 s[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.379 ns" { data[5] hexd[1]~65 s~1365 s~1366 s[1] } { 0.000ns 0.530ns 3.104ns 0.422ns 1.429ns } { 0.000ns 0.590ns 0.590ns 0.590ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}