📄 adc.tan.rpt
字号:
; N/A ; None ; 16.801 ns ; data[2] ; s[1] ; clk ;
; N/A ; None ; 16.760 ns ; data[5] ; s[2] ; clk ;
; N/A ; None ; 16.724 ns ; data[1] ; s[6] ; clk ;
; N/A ; None ; 16.702 ns ; data[1] ; s[0] ; clk ;
; N/A ; None ; 16.615 ns ; data[5] ; s[4] ; clk ;
; N/A ; None ; 16.614 ns ; data[5] ; s[3] ; clk ;
; N/A ; None ; 16.606 ns ; data[5] ; s[5] ; clk ;
; N/A ; None ; 16.582 ns ; data[3] ; s[6] ; clk ;
; N/A ; None ; 16.559 ns ; data[3] ; s[0] ; clk ;
; N/A ; None ; 16.526 ns ; data[6] ; s[2] ; clk ;
; N/A ; None ; 16.519 ns ; data[0] ; s[1] ; clk ;
; N/A ; None ; 16.493 ns ; data[2] ; s[6] ; clk ;
; N/A ; None ; 16.470 ns ; data[2] ; s[0] ; clk ;
; N/A ; None ; 16.450 ns ; data[7] ; s[2] ; clk ;
; N/A ; None ; 16.384 ns ; data[6] ; s[4] ; clk ;
; N/A ; None ; 16.383 ns ; data[6] ; s[3] ; clk ;
; N/A ; None ; 16.372 ns ; data[6] ; s[5] ; clk ;
; N/A ; None ; 16.307 ns ; data[7] ; s[4] ; clk ;
; N/A ; None ; 16.306 ns ; data[7] ; s[3] ; clk ;
; N/A ; None ; 16.296 ns ; data[7] ; s[5] ; clk ;
; N/A ; None ; 16.259 ns ; data[4] ; s[2] ; clk ;
; N/A ; None ; 16.179 ns ; data[0] ; s[0] ; clk ;
; N/A ; None ; 16.110 ns ; data[4] ; s[5] ; clk ;
; N/A ; None ; 16.103 ns ; data[4] ; s[4] ; clk ;
; N/A ; None ; 16.101 ns ; data[4] ; s[3] ; clk ;
; N/A ; None ; 16.018 ns ; data[1] ; s[2] ; clk ;
; N/A ; None ; 15.875 ns ; data[3] ; s[2] ; clk ;
; N/A ; None ; 15.873 ns ; data[1] ; s[4] ; clk ;
; N/A ; None ; 15.872 ns ; data[1] ; s[3] ; clk ;
; N/A ; None ; 15.864 ns ; data[1] ; s[5] ; clk ;
; N/A ; None ; 15.785 ns ; data[2] ; s[2] ; clk ;
; N/A ; None ; 15.732 ns ; data[3] ; s[4] ; clk ;
; N/A ; None ; 15.731 ns ; data[3] ; s[3] ; clk ;
; N/A ; None ; 15.721 ns ; data[3] ; s[5] ; clk ;
; N/A ; None ; 15.643 ns ; data[2] ; s[4] ; clk ;
; N/A ; None ; 15.642 ns ; data[2] ; s[3] ; clk ;
; N/A ; None ; 15.631 ns ; data[2] ; s[5] ; clk ;
; N/A ; None ; 15.508 ns ; data[0] ; s[2] ; clk ;
; N/A ; None ; 15.359 ns ; data[0] ; s[5] ; clk ;
; N/A ; None ; 15.352 ns ; data[0] ; s[4] ; clk ;
; N/A ; None ; 15.350 ns ; data[0] ; s[3] ; clk ;
; N/A ; None ; 14.938 ns ; clkcount[0] ; s[1] ; clk ;
; N/A ; None ; 14.768 ns ; clkcount[0] ; s[6] ; clk ;
; N/A ; None ; 14.608 ns ; clkcount[0] ; s[0] ; clk ;
; N/A ; None ; 13.924 ns ; clkcount[0] ; s[2] ; clk ;
; N/A ; None ; 13.779 ns ; clkcount[0] ; s[4] ; clk ;
; N/A ; None ; 13.778 ns ; clkcount[0] ; s[3] ; clk ;
; N/A ; None ; 13.770 ns ; clkcount[0] ; s[5] ; clk ;
; N/A ; None ; 12.010 ns ; rd~reg0 ; rd ; clk ;
; N/A ; None ; 11.926 ns ; wr~reg0 ; wr ; clk ;
; N/A ; None ; 11.924 ns ; cs~reg0 ; cs ; clk ;
; N/A ; None ; 7.397 ns ; clkcount[0] ; scan[1] ; clk ;
; N/A ; None ; 7.397 ns ; clkcount[0] ; scan[0] ; clk ;
+-------+--------------+------------+-------------+---------+------------+
+------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+---------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+---------+---------+----------+
; N/A ; None ; 1.505 ns ; dati[7] ; data[7] ; clk ;
; N/A ; None ; 1.499 ns ; dati[5] ; data[5] ; clk ;
; N/A ; None ; 1.346 ns ; dati[6] ; data[6] ; clk ;
; N/A ; None ; 1.335 ns ; dati[4] ; data[4] ; clk ;
; N/A ; None ; 1.254 ns ; dati[3] ; data[3] ; clk ;
; N/A ; None ; 1.233 ns ; dati[1] ; data[1] ; clk ;
; N/A ; None ; 1.211 ns ; dati[2] ; data[2] ; clk ;
; N/A ; None ; 1.180 ns ; dati[0] ; data[0] ; clk ;
+---------------+-------------+-----------+---------+---------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Wed Apr 30 11:31:06 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adc -c adc --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clkcount[3]" as buffer
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "rd~reg0" and destination register "data[2]"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.449 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N7; Fanout = 10; REG Node = 'rd~reg0'
Info: 2: + IC(0.582 ns) + CELL(0.867 ns) = 1.449 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'data[2]'
Info: Total cell delay = 0.867 ns ( 59.83 % )
Info: Total interconnect delay = 0.582 ns ( 40.17 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 8.171 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount[3]'
Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N5; Fanout = 1; REG Node = 'data[2]'
Info: Total cell delay = 3.115 ns ( 38.12 % )
Info: Total interconnect delay = 5.056 ns ( 61.88 % )
Info: - Longest clock path from clock "clk" to source register is 8.171 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount[3]'
Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N7; Fanout = 10; REG Node = 'rd~reg0'
Info: Total cell delay = 3.115 ns ( 38.12 % )
Info: Total interconnect delay = 5.056 ns ( 61.88 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "data[0]" (data pin = "dati[0]", clock pin = "clk") is -1.128 ns
Info: + Longest pin to register delay is 7.006 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_114; Fanout = 1; PIN Node = 'dati[0]'
Info: 2: + IC(5.416 ns) + CELL(0.115 ns) = 7.006 ns; Loc. = LC_X34_Y2_N4; Fanout = 1; REG Node = 'data[0]'
Info: Total cell delay = 1.590 ns ( 22.69 % )
Info: Total interconnect delay = 5.416 ns ( 77.31 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "clk" to destination register is 8.171 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount[3]'
Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N4; Fanout = 1; REG Node = 'data[0]'
Info: Total cell delay = 3.115 ns ( 38.12 % )
Info: Total interconnect delay = 5.056 ns ( 61.88 % )
Info: tco from clock "clk" to destination pin "s[1]" through register "data[5]" is 17.774 ns
Info: + Longest clock path from clock "clk" to source register is 8.171 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount[3]'
Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N1; Fanout = 2; REG Node = 'data[5]'
Info: Total cell delay = 3.115 ns ( 38.12 % )
Info: Total interconnect delay = 5.056 ns ( 61.88 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 9.379 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N1; Fanout = 2; REG Node = 'data[5]'
Info: 2: + IC(0.530 ns) + CELL(0.590 ns) = 1.120 ns; Loc. = LC_X34_Y2_N3; Fanout = 9; COMB Node = 'hexd[1]~65'
Info: 3: + IC(3.104 ns) + CELL(0.590 ns) = 4.814 ns; Loc. = LC_X34_Y19_N9; Fanout = 1; COMB Node = 's~1365'
Info: 4: + IC(0.422 ns) + CELL(0.590 ns) = 5.826 ns; Loc. = LC_X34_Y19_N4; Fanout = 1; COMB Node = 's~1366'
Info: 5: + IC(1.429 ns) + CELL(2.124 ns) = 9.379 ns; Loc. = PIN_179; Fanout = 0; PIN Node = 's[1]'
Info: Total cell delay = 3.894 ns ( 41.52 % )
Info: Total interconnect delay = 5.485 ns ( 58.48 % )
Info: th for register "data[7]" (data pin = "dati[7]", clock pin = "clk") is 1.505 ns
Info: + Longest clock path from clock "clk" to destination register is 8.171 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X11_Y6_N4; Fanout = 14; REG Node = 'clkcount[3]'
Info: 3: + IC(4.333 ns) + CELL(0.711 ns) = 8.171 ns; Loc. = LC_X34_Y2_N0; Fanout = 2; REG Node = 'data[7]'
Info: Total cell delay = 3.115 ns ( 38.12 % )
Info: Total interconnect delay = 5.056 ns ( 61.88 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 6.681 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; PIN Node = 'dati[7]'
Info: 2: + IC(5.097 ns) + CELL(0.115 ns) = 6.681 ns; Loc. = LC_X34_Y2_N0; Fanout = 2; REG Node = 'data[7]'
Info: Total cell delay = 1.584 ns ( 23.71 % )
Info: Total interconnect delay = 5.097 ns ( 76.29 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Wed Apr 30 11:31:07 2008
Info: Elapsed time: 00:00:01
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