jsai.tan.qmsg

基于北京革新公司出品的EDA实验工具箱的LED扫描显示程序。能够显示8位数字。编译环境为quartusll.5.1版本。fpga芯片为EP18CQ240C6

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SysClk register fcount\[1\] register fcount\[4\] 267.59 MHz 3.737 ns Internal " "Info: Clock \"SysClk\" has Internal fmax of 267.59 MHz between source register \"fcount\[1\]\" and destination register \"fcount\[4\]\" (period= 3.737 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.476 ns + Longest register register " "Info: + Longest register to register delay is 3.476 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fcount\[1\] 1 REG LC_X24_Y4_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y4_N8; Fanout = 4; REG Node = 'fcount\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "" { fcount[1] } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.590 ns) 1.353 ns rtl~48 2 COMB LC_X24_Y4_N5 2 " "Info: 2: + IC(0.763 ns) + CELL(0.590 ns) = 1.353 ns; Loc. = LC_X24_Y4_N5; Fanout = 2; COMB Node = 'rtl~48'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "1.353 ns" { fcount[1] rtl~48 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.442 ns) 2.192 ns rtl~0 3 COMB LC_X24_Y4_N7 1 " "Info: 3: + IC(0.397 ns) + CELL(0.442 ns) = 2.192 ns; Loc. = LC_X24_Y4_N7; Fanout = 1; COMB Node = 'rtl~0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "0.839 ns" { rtl~48 rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.607 ns) 3.476 ns fcount\[4\] 4 REG LC_X25_Y4_N9 4 " "Info: 4: + IC(0.677 ns) + CELL(0.607 ns) = 3.476 ns; Loc. = LC_X25_Y4_N9; Fanout = 4; REG Node = 'fcount\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "1.284 ns" { rtl~0 fcount[4] } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.639 ns ( 47.15 % ) " "Info: Total cell delay = 1.639 ns ( 47.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.837 ns ( 52.85 % ) " "Info: Total interconnect delay = 1.837 ns ( 52.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "3.476 ns" { fcount[1] rtl~48 rtl~0 fcount[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.476 ns" { fcount[1] rtl~48 rtl~0 fcount[4] } { 0.000ns 0.763ns 0.397ns 0.677ns } { 0.000ns 0.590ns 0.442ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SysClk destination 2.910 ns + Shortest register " "Info: + Shortest clock path from clock \"SysClk\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SysClk 1 CLK PIN_152 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 9; CLK Node = 'SysClk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "" { SysClk } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns fcount\[4\] 2 REG LC_X25_Y4_N9 4 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X25_Y4_N9; Fanout = 4; REG Node = 'fcount\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "1.441 ns" { SysClk fcount[4] } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.91 % ) " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns ( 25.09 % ) " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "2.910 ns" { SysClk fcount[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { SysClk SysClk~out0 fcount[4] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SysClk source 2.910 ns - Longest register " "Info: - Longest clock path from clock \"SysClk\" to source register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SysClk 1 CLK PIN_152 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 9; CLK Node = 'SysClk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "" { SysClk } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns fcount\[1\] 2 REG LC_X24_Y4_N8 4 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X24_Y4_N8; Fanout = 4; REG Node = 'fcount\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "1.441 ns" { SysClk fcount[1] } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.91 % ) " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns ( 25.09 % ) " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "2.910 ns" { SysClk fcount[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { SysClk SysClk~out0 fcount[1] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "2.910 ns" { SysClk fcount[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { SysClk SysClk~out0 fcount[4] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "2.910 ns" { SysClk fcount[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { SysClk SysClk~out0 fcount[1] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "3.476 ns" { fcount[1] rtl~48 rtl~0 fcount[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.476 ns" { fcount[1] rtl~48 rtl~0 fcount[4] } { 0.000ns 0.763ns 0.397ns 0.677ns } { 0.000ns 0.590ns 0.442ns 0.607ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "2.910 ns" { SysClk fcount[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { SysClk SysClk~out0 fcount[4] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "2.910 ns" { SysClk fcount[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.910 ns" { SysClk SysClk~out0 fcount[1] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SysClk SCAN\[0\] count\[2\] 17.870 ns register " "Info: tco from clock \"SysClk\" to destination pin \"SCAN\[0\]\" through register \"count\[2\]\" is 17.870 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SysClk source 8.666 ns + Longest register " "Info: + Longest clock path from clock \"SysClk\" to source register is 8.666 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SysClk 1 CLK PIN_152 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 9; CLK Node = 'SysClk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "" { SysClk } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.935 ns) 3.134 ns q1 2 REG LC_X24_Y4_N7 4 " "Info: 2: + IC(0.730 ns) + CELL(0.935 ns) = 3.134 ns; Loc. = LC_X24_Y4_N7; Fanout = 4; REG Node = 'q1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "1.665 ns" { SysClk q1 } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.821 ns) + CELL(0.711 ns) 8.666 ns count\[2\] 3 REG LC_X34_Y20_N7 15 " "Info: 3: + IC(4.821 ns) + CELL(0.711 ns) = 8.666 ns; Loc. = LC_X34_Y20_N7; Fanout = 15; REG Node = 'count\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "5.532 ns" { q1 count[2] } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 35.95 % ) " "Info: Total cell delay = 3.115 ns ( 35.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.551 ns ( 64.05 % ) " "Info: Total interconnect delay = 5.551 ns ( 64.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "8.666 ns" { SysClk q1 count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.666 ns" { SysClk SysClk~out0 q1 count[2] } { 0.000ns 0.000ns 0.730ns 4.821ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.980 ns + Longest register pin " "Info: + Longest register to pin delay is 8.980 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[2\] 1 REG LC_X34_Y20_N7 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y20_N7; Fanout = 15; REG Node = 'count\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "" { count[2] } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.275 ns) + CELL(0.590 ns) 4.865 ns Mux~448 2 COMB LC_X19_Y1_N8 1 " "Info: 2: + IC(4.275 ns) + CELL(0.590 ns) = 4.865 ns; Loc. = LC_X19_Y1_N8; Fanout = 1; COMB Node = 'Mux~448'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "4.865 ns" { count[2] Mux~448 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.007 ns) + CELL(2.108 ns) 8.980 ns SCAN\[0\] 3 PIN PIN_83 0 " "Info: 3: + IC(2.007 ns) + CELL(2.108 ns) = 8.980 ns; Loc. = PIN_83; Fanout = 0; PIN Node = 'SCAN\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "4.115 ns" { Mux~448 SCAN[0] } "NODE_NAME" } "" } } { "jsai.vhd" "" { Text "D:/led显示/jsai.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns ( 30.04 % ) " "Info: Total cell delay = 2.698 ns ( 30.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.282 ns ( 69.96 % ) " "Info: Total interconnect delay = 6.282 ns ( 69.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "8.980 ns" { count[2] Mux~448 SCAN[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.980 ns" { count[2] Mux~448 SCAN[0] } { 0.000ns 4.275ns 2.007ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "8.666 ns" { SysClk q1 count[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.666 ns" { SysClk SysClk~out0 q1 count[2] } { 0.000ns 0.000ns 0.730ns 4.821ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jsai" "UNKNOWN" "V1" "D:/led显示/db/jsai.quartus_db" { Floorplan "D:/led显示/" "" "8.980 ns" { count[2] Mux~448 SCAN[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.980 ns" { count[2] Mux~448 SCAN[0] } { 0.000ns 4.275ns 2.007ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 01 10:44:52 2008 " "Info: Processing ended: Thu May 01 10:44:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}