jsai.map.rpt

基于北京革新公司出品的EDA实验工具箱的LED扫描显示程序。能够显示8位数字。编译环境为quartusll.5.1版本。fpga芯片为EP18CQ240C6

; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; jsai.vhd                         ; yes             ; User VHDL File  ; D:/led显示/jsai.vhd          ;
+----------------------------------+-----------------+-----------------+------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Total logic elements                        ; 37       ;
;     -- Combinational with no register       ; 25       ;
;     -- Register only                        ; 8        ;
;     -- Combinational with a register        ; 4        ;
;                                             ;          ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 2        ;
;     -- 3 input functions                    ; 15       ;
;     -- 2 input functions                    ; 10       ;
;     -- 1 input functions                    ; 2        ;
;     -- 0 input functions                    ; 0        ;
;         -- Combinational cells for routing  ; 0        ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 30       ;
;     -- arithmetic mode                      ; 7        ;
;     -- qfbk mode                            ; 0        ;
;     -- register cascade mode                ; 0        ;
;     -- synchronous clear/load mode          ; 0        ;
;     -- asynchronous clear/load mode         ; 0        ;
;                                             ;          ;
; Total registers                             ; 12       ;
; Total logic cells in carry chains           ; 8        ;
; I/O pins                                    ; 18       ;
; Maximum fan-out node                        ; count[0] ;
; Maximum fan-out                             ; 17       ;
; Total fan-out                               ; 111      ;
; Average fan-out                             ; 2.02     ;
+---------------------------------------------+----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |jsai                      ; 37 (37)     ; 12           ; 0           ; 18   ; 0            ; 25 (25)      ; 8 (8)             ; 4 (4)            ; 8 (8)           ; 0 (0)      ; |jsai               ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 12    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/led显示/jsai.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu May 01 10:44:42 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jsai -c jsai
Info: Found 2 design units, including 1 entities, in source file fenpin.vhd
    Info: Found design unit 1: fenpin-fenpin
    Info: Found entity 1: fenpin
Info: Found 2 design units, including 1 entities, in source file jsai.vhd
    Info: Found design unit 1: jsai-a
    Info: Found entity 1: jsai
Info: Elaborating entity "jsai" for the top level hierarchy
Info (10425): VHDL Case Statement information at jsai.vhd(53): OTHERS choice is never selected
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SEG7[7]" stuck at GND
Info: Implemented 55 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 17 output pins
    Info: Implemented 37 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu May 01 10:44:44 2008
    Info: Elapsed time: 00:00:02