jsai.fit.rpt

基于北京革新公司出品的EDA实验工具箱的LED扫描显示程序。能够显示8位数字。编译环境为quartusll.5.1版本。fpga芯片为EP18CQ240C6

; Perform Register Duplication                         ; Off                ; Off                            ;
; Perform Register Retiming                            ; Off                ; Off                            ;
; Perform Asynchronous Signal Pipelining               ; Off                ; Off                            ;
; Fitter Effort                                        ; Auto Fit           ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal             ; Normal                         ;
; Logic Cell Insertion - Logic Duplication             ; Auto               ; Auto                           ;
; Auto Register Duplication                            ; Off                ; Off                            ;
; Auto Global Clock                                    ; On                 ; On                             ;
; Auto Global Register Control Signals                 ; On                 ; On                             ;
+------------------------------------------------------+--------------------+--------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/led显示/jsai.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/led显示/jsai.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 34 / 5,980 ( < 1 % ) ;
;     -- Combinational with no register       ; 22                   ;
;     -- Register only                        ; 5                    ;
;     -- Combinational with a register        ; 7                    ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 2                    ;
;     -- 3 input functions                    ; 15                   ;
;     -- 2 input functions                    ; 10                   ;
;     -- 1 input functions                    ; 5                    ;
;     -- 0 input functions                    ; 2                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 27                   ;
;     -- arithmetic mode                      ; 7                    ;
;     -- qfbk mode                            ; 2                    ;
;     -- register cascade mode                ; 0                    ;
;     -- synchronous clear/load mode          ; 4                    ;
;     -- asynchronous clear/load mode         ; 0                    ;
;                                             ;                      ;
; Total LABs                                  ; 4 / 598 ( < 1 % )    ;
; Logic elements in carry chains              ; 8                    ;
; User inserted logic elements                ; 0                    ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 18 / 185 ( 10 % )    ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )       ;
; Global signals                              ; 2                    ;
; M4Ks                                        ; 0 / 20 ( 0 % )       ;
; Total memory bits                           ; 0 / 92,160 ( 0 % )   ;
; Total RAM block bits                        ; 0 / 92,160 ( 0 % )   ;
; PLLs                                        ; 0 / 2 ( 0 % )        ;
; Global clocks                               ; 2 / 8 ( 25 % )       ;
; Maximum fan-out node                        ; count[0]             ;
; Maximum fan-out                             ; 17                   ;
; Highest non-global fan-out signal           ; count[0]             ;
; Highest non-global fan-out                  ; 17                   ;
; Total fan-out                               ; 110                  ;
; Average fan-out                             ; 2.04                 ;
+---------------------------------------------+----------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                   ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; SysClk ; 152   ; 3        ; 35           ; 12           ; 2           ; 9                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                      ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load        ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; SCAN[0] ; 83    ; 4        ; 14           ; 0            ; 2           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; Unspecified ;