jsai.tan.rpt

基于北京革新公司出品的EDA实验工具箱的LED扫描显示程序。能够显示8位数字。编译环境为quartusll.5.1版本。fpga芯片为EP18CQ240C6

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[2] ; fcount[2] ; SysClk     ; SysClk   ; None                        ; None                      ; 1.992 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[2] ; q1        ; SysClk     ; SysClk   ; None                        ; None                      ; 1.946 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[0] ; q1        ; SysClk     ; SysClk   ; None                        ; None                      ; 1.868 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[7] ; fcount[7] ; SysClk     ; SysClk   ; None                        ; None                      ; 1.697 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[0] ; fcount[0] ; SysClk     ; SysClk   ; None                        ; None                      ; 1.675 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[3] ; q1        ; SysClk     ; SysClk   ; None                        ; None                      ; 1.382 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[7] ; q1        ; SysClk     ; SysClk   ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0]  ; count[1]  ; SysClk     ; SysClk   ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0]  ; count[2]  ; SysClk     ; SysClk   ; None                        ; None                      ; 1.287 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[5] ; q1        ; SysClk     ; SysClk   ; None                        ; None                      ; 1.266 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[2]  ; count[2]  ; SysClk     ; SysClk   ; None                        ; None                      ; 1.095 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[4] ; q1        ; SysClk     ; SysClk   ; None                        ; None                      ; 1.046 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1]  ; count[2]  ; SysClk     ; SysClk   ; None                        ; None                      ; 1.044 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1]  ; count[1]  ; SysClk     ; SysClk   ; None                        ; None                      ; 1.033 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0]  ; count[0]  ; SysClk     ; SysClk   ; None                        ; None                      ; 1.000 ns                ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To      ; From Clock ;
+-------+--------------+------------+----------+---------+------------+
; N/A   ; None         ; 17.870 ns  ; count[2] ; SCAN[0] ; SysClk     ;
; N/A   ; None         ; 17.867 ns  ; count[2] ; SCAN[1] ; SysClk     ;
; N/A   ; None         ; 17.855 ns  ; count[1] ; SCAN[1] ; SysClk     ;
; N/A   ; None         ; 17.852 ns  ; count[1] ; SCAN[0] ; SysClk     ;
; N/A   ; None         ; 17.548 ns  ; count[0] ; SCAN[0] ; SysClk     ;
; N/A   ; None         ; 17.547 ns  ; count[0] ; SCAN[1] ; SysClk     ;
; N/A   ; None         ; 17.546 ns  ; count[2] ; SCAN[3] ; SysClk     ;
; N/A   ; None         ; 17.542 ns  ; count[2] ; SCAN[5] ; SysClk     ;
; N/A   ; None         ; 17.533 ns  ; count[2] ; SCAN[4] ; SysClk     ;
; N/A   ; None         ; 17.526 ns  ; count[1] ; SCAN[4] ; SysClk     ;
; N/A   ; None         ; 17.519 ns  ; count[1] ; SCAN[3] ; SysClk     ;
; N/A   ; None         ; 17.510 ns  ; count[1] ; SCAN[5] ; SysClk     ;
; N/A   ; None         ; 17.224 ns  ; count[0] ; SCAN[3] ; SysClk     ;
; N/A   ; None         ; 17.220 ns  ; count[0] ; SCAN[5] ; SysClk     ;
; N/A   ; None         ; 17.215 ns  ; count[0] ; SCAN[4] ; SysClk     ;
; N/A   ; None         ; 17.101 ns  ; count[2] ; SCAN[6] ; SysClk     ;
; N/A   ; None         ; 17.089 ns  ; count[1] ; SCAN[7] ; SysClk     ;
; N/A   ; None         ; 17.087 ns  ; count[2] ; SCAN[7] ; SysClk     ;
; N/A   ; None         ; 17.079 ns  ; count[1] ; SCAN[6] ; SysClk     ;
; N/A   ; None         ; 16.793 ns  ; count[0] ; SCAN[2] ; SysClk     ;
; N/A   ; None         ; 16.778 ns  ; count[0] ; SCAN[6] ; SysClk     ;
; N/A   ; None         ; 16.770 ns  ; count[0] ; SCAN[7] ; SysClk     ;
; N/A   ; None         ; 16.572 ns  ; count[2] ; SCAN[2] ; SysClk     ;
; N/A   ; None         ; 16.496 ns  ; count[1] ; SCAN[2] ; SysClk     ;
; N/A   ; None         ; 13.694 ns  ; count[0] ; SEG7[6] ; SysClk     ;
; N/A   ; None         ; 13.658 ns  ; count[0] ; SEG7[0] ; SysClk     ;
; N/A   ; None         ; 13.476 ns  ; count[2] ; SEG7[6] ; SysClk     ;
; N/A   ; None         ; 13.450 ns  ; count[2] ; SEG7[0] ; SysClk     ;
; N/A   ; None         ; 13.404 ns  ; count[1] ; SEG7[6] ; SysClk     ;
; N/A   ; None         ; 13.391 ns  ; count[1] ; SEG7[0] ; SysClk     ;
; N/A   ; None         ; 13.382 ns  ; count[0] ; SEG7[4] ; SysClk     ;
; N/A   ; None         ; 13.373 ns  ; count[0] ; SEG7[5] ; SysClk     ;
; N/A   ; None         ; 13.373 ns  ; count[0] ; SEG7[3] ; SysClk     ;
; N/A   ; None         ; 13.238 ns  ; count[0] ; SEG7[2] ; SysClk     ;
; N/A   ; None         ; 13.228 ns  ; count[0] ; SEG7[1] ; SysClk     ;
; N/A   ; None         ; 13.160 ns  ; count[2] ; SEG7[4] ; SysClk     ;
; N/A   ; None         ; 13.155 ns  ; count[2] ; SEG7[5] ; SysClk     ;
; N/A   ; None         ; 13.152 ns  ; count[2] ; SEG7[3] ; SysClk     ;
; N/A   ; None         ; 13.088 ns  ; count[1] ; SEG7[5] ; SysClk     ;
; N/A   ; None         ; 13.085 ns  ; count[1] ; SEG7[4] ; SysClk     ;
; N/A   ; None         ; 13.077 ns  ; count[1] ; SEG7[3] ; SysClk     ;
; N/A   ; None         ; 13.017 ns  ; count[2] ; SEG7[2] ; SysClk     ;
; N/A   ; None         ; 13.012 ns  ; count[2] ; SEG7[1] ; SysClk     ;
; N/A   ; None         ; 12.949 ns  ; count[1] ; SEG7[1] ; SysClk     ;
; N/A   ; None         ; 12.941 ns  ; count[1] ; SEG7[2] ; SysClk     ;
; N/A   ; None         ; 8.882 ns   ; q1       ; q       ; SysClk     ;
+-------+--------------+------------+----------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu May 01 10:44:52 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jsai -c jsai --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "SysClk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "q1" as buffer
Info: Clock "SysClk" has Internal fmax of 267.59 MHz between source register "fcount[1]" and destination register "fcount[4]" (period= 3.737 ns)
    Info: + Longest register to register delay is 3.476 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y4_N8; Fanout = 4; REG Node = 'fcount[1]'
        Info: 2: + IC(0.763 ns) + CELL(0.590 ns) = 1.353 ns; Loc. = LC_X24_Y4_N5; Fanout = 2; COMB Node = 'rtl~48'
        Info: 3: + IC(0.397 ns) + CELL(0.442 ns) = 2.192 ns; Loc. = LC_X24_Y4_N7; Fanout = 1; COMB Node = 'rtl~0'
        Info: 4: + IC(0.677 ns) + CELL(0.607 ns) = 3.476 ns; Loc. = LC_X25_Y4_N9; Fanout = 4; REG Node = 'fcount[4]'
        Info: Total cell delay = 1.639 ns ( 47.15 % )
        Info: Total interconnect delay = 1.837 ns ( 52.85 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "SysClk" to destination register is 2.910 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 9; CLK Node = 'SysClk'
            Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X25_Y4_N9; Fanout = 4; REG Node = 'fcount[4]'
            Info: Total cell delay = 2.180 ns ( 74.91 % )
            Info: Total interconnect delay = 0.730 ns ( 25.09 % )
        Info: - Longest clock path from clock "SysClk" to source register is 2.910 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 9; CLK Node = 'SysClk'
            Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X24_Y4_N8; Fanout = 4; REG Node = 'fcount[1]'
            Info: Total cell delay = 2.180 ns ( 74.91 % )
            Info: Total interconnect delay = 0.730 ns ( 25.09 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "SysClk" to destination pin "SCAN[0]" through register "count[2]" is 17.870 ns
    Info: + Longest clock path from clock "SysClk" to source register is 8.666 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 9; CLK Node = 'SysClk'
        Info: 2: + IC(0.730 ns) + CELL(0.935 ns) = 3.134 ns; Loc. = LC_X24_Y4_N7; Fanout = 4; REG Node = 'q1'
        Info: 3: + IC(4.821 ns) + CELL(0.711 ns) = 8.666 ns; Loc. = LC_X34_Y20_N7; Fanout = 15; REG Node = 'count[2]'
        Info: Total cell delay = 3.115 ns ( 35.95 % )
        Info: Total interconnect delay = 5.551 ns ( 64.05 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 8.980 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y20_N7; Fanout = 15; REG Node = 'count[2]'
        Info: 2: + IC(4.275 ns) + CELL(0.590 ns) = 4.865 ns; Loc. = LC_X19_Y1_N8; Fanout = 1; COMB Node = 'Mux~448'
        Info: 3: + IC(2.007 ns) + CELL(2.108 ns) = 8.980 ns; Loc. = PIN_83; Fanout = 0; PIN Node = 'SCAN[0]'
        Info: Total cell delay = 2.698 ns ( 30.04 % )
        Info: Total interconnect delay = 6.282 ns ( 69.96 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu May 01 10:44:52 2008
    Info: Elapsed time: 00:00:01