jianpan.fit.qmsg

基于北京革新公司出品的EDA实验工具箱的键盘扫描与同步显示程序。编译环境为quartusll.5.1版本。fpga芯片为EP18CQ240C6

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.533 ns register register " "Info: Estimated most critical path is register to register delay of 2.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LAB_X31_Y16 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X31_Y16; Fanout = 14; REG Node = 'count\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { count[0] } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.224 ns) + CELL(0.309 ns) 2.533 ns KBRow\[2\]~reg0 2 REG LAB_X31_Y7 1 " "Info: 2: + IC(2.224 ns) + CELL(0.309 ns) = 2.533 ns; Loc. = LAB_X31_Y7; Fanout = 1; REG Node = 'KBRow\[2\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.533 ns" { count[0] KBRow[2]~reg0 } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 12.20 % ) " "Info: Total cell delay = 0.309 ns ( 12.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.224 ns ( 87.80 % ) " "Info: Total interconnect delay = 2.224 ns ( 87.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.533 ns" { count[0] KBRow[2]~reg0 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "8 " "Warning: Following 8 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[0\] VCC " "Info: Pin scan\[0\] has VCC driving its datain port" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "scan\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { scan[0] } "NODE_NAME" } "" } } { "D:/jianpan/jianpan/jianpan.fld" "" { Floorplan "D:/jianpan/jianpan/jianpan.fld" "" "" { scan[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[1\] GND " "Info: Pin scan\[1\] has GND driving its datain port" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "scan\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { scan[1] } "NODE_NAME" } "" } } { "D:/jianpan/jianpan/jianpan.fld" "" { Floorplan "D:/jianpan/jianpan/jianpan.fld" "" "" { scan[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[2\] GND " "Info: Pin scan\[2\] has GND driving its datain port" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "scan\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { scan[2] } "NODE_NAME" } "" } } { "D:/jianpan/jianpan/jianpan.fld" "" { Floorplan "D:/jianpan/jianpan/jianpan.fld" "" "" { scan[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[3\] GND " "Info: Pin scan\[3\] has GND driving its datain port" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "scan\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { scan[3] } "NODE_NAME" } "" } } { "D:/jianpan/jianpan/jianpan.fld" "" { Floorplan "D:/jianpan/jianpan/jianpan.fld" "" "" { scan[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[4\] GND " "Info: Pin scan\[4\] has GND driving its datain port" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "scan\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { scan[4] } "NODE_NAME" } "" } } { "D:/jianpan/jianpan/jianpan.fld" "" { Floorplan "D:/jianpan/jianpan/jianpan.fld" "" "" { scan[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[5\] GND " "Info: Pin scan\[5\] has GND driving its datain port" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "scan\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { scan[5] } "NODE_NAME" } "" } } { "D:/jianpan/jianpan/jianpan.fld" "" { Floorplan "D:/jianpan/jianpan/jianpan.fld" "" "" { scan[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[6\] GND " "Info: Pin scan\[6\] has GND driving its datain port" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "scan\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { scan[6] } "NODE_NAME" } "" } } { "D:/jianpan/jianpan/jianpan.fld" "" { Floorplan "D:/jianpan/jianpan/jianpan.fld" "" "" { scan[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "scan\[7\] GND " "Info: Pin scan\[7\] has GND driving its datain port" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "scan\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { scan[7] } "NODE_NAME" } "" } } { "D:/jianpan/jianpan/jianpan.fld" "" { Floorplan "D:/jianpan/jianpan/jianpan.fld" "" "" { scan[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 01 11:54:10 2008 " "Info: Processing ended: Thu May 01 11:54:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}