jianpan.map.qmsg

基于北京革新公司出品的EDA实验工具箱的键盘扫描与同步显示程序。编译环境为quartusll.5.1版本。fpga芯片为EP18CQ240C6

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 01 11:54:04 2008 " "Info: Processing started: Thu May 01 11:54:04 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jianpan -c jianpan " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jianpan -c jianpan" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jianpan.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file jianpan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 jianpan-bev " "Info: Found design unit 1: jianpan-bev" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 jianpan " "Info: Found entity 1: jianpan" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "jianpan " "Info: Elaborating entity \"jianpan\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "jianpan.vhd(40) " "Info (10425): VHDL Case Statement information at jianpan.vhd(40): OTHERS choice is never selected" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 40 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "jianpan.vhd(84) " "Info (10425): VHDL Case Statement information at jianpan.vhd(84): OTHERS choice is never selected" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 84 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "sta\[0\] count\[0\] " "Info: Duplicate register \"sta\[0\]\" merged to single register \"count\[0\]\", power-up level changed" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 30 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[0\] VCC " "Warning: Pin \"scan\[0\]\" stuck at VCC" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[1\] GND " "Warning: Pin \"scan\[1\]\" stuck at GND" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[2\] GND " "Warning: Pin \"scan\[2\]\" stuck at GND" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[3\] GND " "Warning: Pin \"scan\[3\]\" stuck at GND" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[4\] GND " "Warning: Pin \"scan\[4\]\" stuck at GND" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[5\] GND " "Warning: Pin \"scan\[5\]\" stuck at GND" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[6\] GND " "Warning: Pin \"scan\[6\]\" stuck at GND" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "scan\[7\] GND " "Warning: Pin \"scan\[7\]\" stuck at GND" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 12 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "56 " "Info: Implemented 56 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "31 " "Info: Implemented 31 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 01 11:54:06 2008 " "Info: Processing ended: Thu May 01 11:54:06 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}