jianpan.tan.qmsg

基于北京革新公司出品的EDA实验工具箱的键盘扫描与同步显示程序。编译环境为quartusll.5.1版本。fpga芯片为EP18CQ240C6

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register sta\[1\] seg7\[1\]~reg0 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"sta\[1\]\" and destination register \"seg7\[1\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.861 ns + Longest register register " "Info: + Longest register to register delay is 2.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sta\[1\] 1 REG LC_X31_Y16_N7 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y16_N7; Fanout = 13; REG Node = 'sta\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { sta[1] } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.402 ns) + CELL(0.292 ns) 1.694 ns Mux~546 2 COMB LC_X31_Y16_N2 1 " "Info: 2: + IC(1.402 ns) + CELL(0.292 ns) = 1.694 ns; Loc. = LC_X31_Y16_N2; Fanout = 1; COMB Node = 'Mux~546'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "1.694 ns" { sta[1] Mux~546 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.738 ns) 2.861 ns seg7\[1\]~reg0 3 REG LC_X31_Y16_N3 1 " "Info: 3: + IC(0.429 ns) + CELL(0.738 ns) = 2.861 ns; Loc. = LC_X31_Y16_N3; Fanout = 1; REG Node = 'seg7\[1\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "1.167 ns" { Mux~546 seg7[1]~reg0 } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.030 ns ( 36.00 % ) " "Info: Total cell delay = 1.030 ns ( 36.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.831 ns ( 64.00 % ) " "Info: Total interconnect delay = 1.831 ns ( 64.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.861 ns" { sta[1] Mux~546 seg7[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.861 ns" { sta[1] Mux~546 seg7[1]~reg0 } { 0.000ns 1.402ns 0.429ns } { 0.000ns 0.292ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { clk } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns seg7\[1\]~reg0 2 REG LC_X31_Y16_N3 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y16_N3; Fanout = 1; REG Node = 'seg7\[1\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "1.493 ns" { clk seg7[1]~reg0 } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk seg7[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 seg7[1]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { clk } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns sta\[1\] 2 REG LC_X31_Y16_N7 13 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y16_N7; Fanout = 13; REG Node = 'sta\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "1.493 ns" { clk sta[1] } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk sta[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 sta[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk seg7[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 seg7[1]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk sta[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 sta[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.861 ns" { sta[1] Mux~546 seg7[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.861 ns" { sta[1] Mux~546 seg7[1]~reg0 } { 0.000ns 1.402ns 0.429ns } { 0.000ns 0.292ns 0.738ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk seg7[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 seg7[1]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk sta[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 sta[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { seg7[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { seg7[1]~reg0 } {  } {  } } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "seg7\[6\]~reg0 KBCol\[2\] clk 8.301 ns register " "Info: tsu for register \"seg7\[6\]~reg0\" (data pin = \"KBCol\[2\]\", clock pin = \"clk\") is 8.301 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.226 ns + Longest pin register " "Info: + Longest pin to register delay is 11.226 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KBCol\[2\] 1 PIN PIN_134 11 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_134; Fanout = 11; PIN Node = 'KBCol\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { KBCol[2] } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.309 ns) + CELL(0.442 ns) 8.220 ns Mux~528 2 COMB LC_X32_Y15_N5 2 " "Info: 2: + IC(6.309 ns) + CELL(0.442 ns) = 8.220 ns; Loc. = LC_X32_Y15_N5; Fanout = 2; COMB Node = 'Mux~528'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "6.751 ns" { KBCol[2] Mux~528 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.247 ns) + CELL(0.590 ns) 10.057 ns Mux~529 3 COMB LC_X31_Y16_N7 1 " "Info: 3: + IC(1.247 ns) + CELL(0.590 ns) = 10.057 ns; Loc. = LC_X31_Y16_N7; Fanout = 1; COMB Node = 'Mux~529'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "1.837 ns" { Mux~528 Mux~529 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.431 ns) + CELL(0.738 ns) 11.226 ns seg7\[6\]~reg0 4 REG LC_X31_Y16_N1 1 " "Info: 4: + IC(0.431 ns) + CELL(0.738 ns) = 11.226 ns; Loc. = LC_X31_Y16_N1; Fanout = 1; REG Node = 'seg7\[6\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "1.169 ns" { Mux~529 seg7[6]~reg0 } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.239 ns ( 28.85 % ) " "Info: Total cell delay = 3.239 ns ( 28.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.987 ns ( 71.15 % ) " "Info: Total interconnect delay = 7.987 ns ( 71.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "11.226 ns" { KBCol[2] Mux~528 Mux~529 seg7[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.226 ns" { KBCol[2] KBCol[2]~out0 Mux~528 Mux~529 seg7[6]~reg0 } { 0.000ns 0.000ns 6.309ns 1.247ns 0.431ns } { 0.000ns 1.469ns 0.442ns 0.590ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { clk } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns seg7\[6\]~reg0 2 REG LC_X31_Y16_N1 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y16_N1; Fanout = 1; REG Node = 'seg7\[6\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "1.493 ns" { clk seg7[6]~reg0 } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk seg7[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 seg7[6]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "11.226 ns" { KBCol[2] Mux~528 Mux~529 seg7[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.226 ns" { KBCol[2] KBCol[2]~out0 Mux~528 Mux~529 seg7[6]~reg0 } { 0.000ns 0.000ns 6.309ns 1.247ns 0.431ns } { 0.000ns 1.469ns 0.442ns 0.590ns 0.738ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk seg7[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 seg7[6]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7\[5\] seg7\[5\]~reg0 7.330 ns register " "Info: tco from clock \"clk\" to destination pin \"seg7\[5\]\" through register \"seg7\[5\]~reg0\" is 7.330 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { clk } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns seg7\[5\]~reg0 2 REG LC_X31_Y16_N9 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y16_N9; Fanout = 1; REG Node = 'seg7\[5\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "1.493 ns" { clk seg7[5]~reg0 } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk seg7[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 seg7[5]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.144 ns + Longest register pin " "Info: + Longest register to pin delay is 4.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seg7\[5\]~reg0 1 REG LC_X31_Y16_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y16_N9; Fanout = 1; REG Node = 'seg7\[5\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { seg7[5]~reg0 } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.036 ns) + CELL(2.108 ns) 4.144 ns seg7\[5\] 2 PIN PIN_183 0 " "Info: 2: + IC(2.036 ns) + CELL(2.108 ns) = 4.144 ns; Loc. = PIN_183; Fanout = 0; PIN Node = 'seg7\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "4.144 ns" { seg7[5]~reg0 seg7[5] } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 50.87 % ) " "Info: Total cell delay = 2.108 ns ( 50.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.036 ns ( 49.13 % ) " "Info: Total interconnect delay = 2.036 ns ( 49.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "4.144 ns" { seg7[5]~reg0 seg7[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.144 ns" { seg7[5]~reg0 seg7[5] } { 0.000ns 2.036ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk seg7[5]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 seg7[5]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "4.144 ns" { seg7[5]~reg0 seg7[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.144 ns" { seg7[5]~reg0 seg7[5] } { 0.000ns 2.036ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "seg7\[0\]~reg0 KBCol\[2\] clk -5.695 ns register " "Info: th for register \"seg7\[0\]~reg0\" (data pin = \"KBCol\[2\]\", clock pin = \"clk\") is -5.695 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { clk } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns seg7\[0\]~reg0 2 REG LC_X32_Y16_N4 1 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X32_Y16_N4; Fanout = 1; REG Node = 'seg7\[0\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "1.493 ns" { clk seg7[0]~reg0 } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk seg7[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 seg7[0]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.672 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KBCol\[2\] 1 PIN PIN_134 11 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_134; Fanout = 11; PIN Node = 'KBCol\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "" { KBCol[2] } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.349 ns) + CELL(0.114 ns) 7.932 ns Mux~527 2 COMB LC_X32_Y16_N0 4 " "Info: 2: + IC(6.349 ns) + CELL(0.114 ns) = 7.932 ns; Loc. = LC_X32_Y16_N0; Fanout = 4; COMB Node = 'Mux~527'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "6.463 ns" { KBCol[2] Mux~527 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.431 ns) + CELL(0.309 ns) 8.672 ns seg7\[0\]~reg0 3 REG LC_X32_Y16_N4 1 " "Info: 3: + IC(0.431 ns) + CELL(0.309 ns) = 8.672 ns; Loc. = LC_X32_Y16_N4; Fanout = 1; REG Node = 'seg7\[0\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "0.740 ns" { Mux~527 seg7[0]~reg0 } "NODE_NAME" } "" } } { "jianpan.vhd" "" { Text "D:/jianpan/jianpan/jianpan.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.892 ns ( 21.82 % ) " "Info: Total cell delay = 1.892 ns ( 21.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.780 ns ( 78.18 % ) " "Info: Total interconnect delay = 6.780 ns ( 78.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "8.672 ns" { KBCol[2] Mux~527 seg7[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.672 ns" { KBCol[2] KBCol[2]~out0 Mux~527 seg7[0]~reg0 } { 0.000ns 0.000ns 6.349ns 0.431ns } { 0.000ns 1.469ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "2.962 ns" { clk seg7[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 seg7[0]~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "jianpan" "UNKNOWN" "V1" "D:/jianpan/jianpan/db/jianpan.quartus_db" { Floorplan "D:/jianpan/jianpan/" "" "8.672 ns" { KBCol[2] Mux~527 seg7[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.672 ns" { KBCol[2] KBCol[2]~out0 Mux~527 seg7[0]~reg0 } { 0.000ns 0.000ns 6.349ns 0.431ns } { 0.000ns 1.469ns 0.114ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}