jianpan.tan.rpt

基于北京革新公司出品的EDA实验工具箱的键盘扫描与同步显示程序。编译环境为quartusll.5.1版本。fpga芯片为EP18CQ240C6

; N/A   ; None         ; 7.887 ns   ; KBCol[1] ; seg7[0]~reg0 ; clk      ;
; N/A   ; None         ; 7.701 ns   ; KBCol[3] ; seg7[5]~reg0 ; clk      ;
; N/A   ; None         ; 7.558 ns   ; KBCol[1] ; seg7[5]~reg0 ; clk      ;
; N/A   ; None         ; 7.549 ns   ; KBCol[0] ; seg7[5]~reg0 ; clk      ;
; N/A   ; None         ; 7.218 ns   ; KBCol[2] ; seg7[5]~reg0 ; clk      ;
; N/A   ; None         ; 7.182 ns   ; KBCol[3] ; seg7[2]~reg0 ; clk      ;
; N/A   ; None         ; 7.034 ns   ; KBCol[0] ; seg7[2]~reg0 ; clk      ;
; N/A   ; None         ; 7.030 ns   ; KBCol[1] ; seg7[2]~reg0 ; clk      ;
; N/A   ; None         ; 6.688 ns   ; KBCol[2] ; seg7[2]~reg0 ; clk      ;
+-------+--------------+------------+----------+--------------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+---------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To       ; From Clock ;
+-------+--------------+------------+---------------+----------+------------+
; N/A   ; None         ; 7.330 ns   ; seg7[5]~reg0  ; seg7[5]  ; clk        ;
; N/A   ; None         ; 7.327 ns   ; seg7[3]~reg0  ; seg7[3]  ; clk        ;
; N/A   ; None         ; 7.229 ns   ; seg7[1]~reg0  ; seg7[1]  ; clk        ;
; N/A   ; None         ; 7.207 ns   ; KBRow[1]~reg0 ; KBRow[1] ; clk        ;
; N/A   ; None         ; 7.194 ns   ; seg7[2]~reg0  ; seg7[2]  ; clk        ;
; N/A   ; None         ; 7.189 ns   ; seg7[0]~reg0  ; seg7[0]  ; clk        ;
; N/A   ; None         ; 7.173 ns   ; KBRow[0]~reg0 ; KBRow[0] ; clk        ;
; N/A   ; None         ; 7.146 ns   ; KBRow[2]~reg0 ; KBRow[2] ; clk        ;
; N/A   ; None         ; 7.143 ns   ; KBRow[3]~reg0 ; KBRow[3] ; clk        ;
; N/A   ; None         ; 7.021 ns   ; seg7[4]~reg0  ; seg7[4]  ; clk        ;
; N/A   ; None         ; 7.018 ns   ; seg7[6]~reg0  ; seg7[6]  ; clk        ;
+-------+--------------+------------+---------------+----------+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+----------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To           ; To Clock ;
+---------------+-------------+-----------+----------+--------------+----------+
; N/A           ; None        ; -5.695 ns ; KBCol[2] ; seg7[0]~reg0 ; clk      ;
; N/A           ; None        ; -5.731 ns ; KBCol[2] ; seg7[4]~reg0 ; clk      ;
; N/A           ; None        ; -6.026 ns ; KBCol[0] ; seg7[0]~reg0 ; clk      ;
; N/A           ; None        ; -6.035 ns ; KBCol[1] ; seg7[0]~reg0 ; clk      ;
; N/A           ; None        ; -6.039 ns ; KBCol[2] ; seg7[6]~reg0 ; clk      ;
; N/A           ; None        ; -6.066 ns ; KBCol[0] ; seg7[4]~reg0 ; clk      ;
; N/A           ; None        ; -6.071 ns ; KBCol[1] ; seg7[4]~reg0 ; clk      ;
; N/A           ; None        ; -6.159 ns ; KBCol[2] ; seg7[2]~reg0 ; clk      ;
; N/A           ; None        ; -6.178 ns ; KBCol[3] ; seg7[0]~reg0 ; clk      ;
; N/A           ; None        ; -6.217 ns ; KBCol[3] ; seg7[4]~reg0 ; clk      ;
; N/A           ; None        ; -6.329 ns ; KBCol[2] ; seg7[5]~reg0 ; clk      ;
; N/A           ; None        ; -6.367 ns ; KBCol[2] ; seg7[3]~reg0 ; clk      ;
; N/A           ; None        ; -6.383 ns ; KBCol[1] ; seg7[6]~reg0 ; clk      ;
; N/A           ; None        ; -6.389 ns ; KBCol[0] ; seg7[6]~reg0 ; clk      ;
; N/A           ; None        ; -6.503 ns ; KBCol[1] ; seg7[2]~reg0 ; clk      ;
; N/A           ; None        ; -6.509 ns ; KBCol[0] ; seg7[2]~reg0 ; clk      ;
; N/A           ; None        ; -6.537 ns ; KBCol[3] ; seg7[6]~reg0 ; clk      ;
; N/A           ; None        ; -6.657 ns ; KBCol[3] ; seg7[2]~reg0 ; clk      ;
; N/A           ; None        ; -6.673 ns ; KBCol[1] ; seg7[5]~reg0 ; clk      ;
; N/A           ; None        ; -6.679 ns ; KBCol[0] ; seg7[5]~reg0 ; clk      ;
; N/A           ; None        ; -6.690 ns ; KBCol[1] ; seg7[1]~reg0 ; clk      ;
; N/A           ; None        ; -6.711 ns ; KBCol[1] ; seg7[3]~reg0 ; clk      ;
; N/A           ; None        ; -6.717 ns ; KBCol[0] ; seg7[3]~reg0 ; clk      ;
; N/A           ; None        ; -6.777 ns ; KBCol[3] ; seg7[1]~reg0 ; clk      ;
; N/A           ; None        ; -6.794 ns ; KBCol[2] ; seg7[1]~reg0 ; clk      ;
; N/A           ; None        ; -6.797 ns ; KBCol[0] ; seg7[1]~reg0 ; clk      ;
; N/A           ; None        ; -6.827 ns ; KBCol[3] ; seg7[5]~reg0 ; clk      ;
; N/A           ; None        ; -6.865 ns ; KBCol[3] ; seg7[3]~reg0 ; clk      ;
+---------------+-------------+-----------+----------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu May 01 11:54:14 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jianpan -c jianpan --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "sta[1]" and destination register "seg7[1]~reg0"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.861 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y16_N7; Fanout = 13; REG Node = 'sta[1]'
            Info: 2: + IC(1.402 ns) + CELL(0.292 ns) = 1.694 ns; Loc. = LC_X31_Y16_N2; Fanout = 1; COMB Node = 'Mux~546'
            Info: 3: + IC(0.429 ns) + CELL(0.738 ns) = 2.861 ns; Loc. = LC_X31_Y16_N3; Fanout = 1; REG Node = 'seg7[1]~reg0'
            Info: Total cell delay = 1.030 ns ( 36.00 % )
            Info: Total interconnect delay = 1.831 ns ( 64.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.962 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y16_N3; Fanout = 1; REG Node = 'seg7[1]~reg0'
                Info: Total cell delay = 2.180 ns ( 73.60 % )
                Info: Total interconnect delay = 0.782 ns ( 26.40 % )
            Info: - Longest clock path from clock "clk" to source register is 2.962 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'
                Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y16_N7; Fanout = 13; REG Node = 'sta[1]'
                Info: Total cell delay = 2.180 ns ( 73.60 % )
                Info: Total interconnect delay = 0.782 ns ( 26.40 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "seg7[6]~reg0" (data pin = "KBCol[2]", clock pin = "clk") is 8.301 ns
    Info: + Longest pin to register delay is 11.226 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_134; Fanout = 11; PIN Node = 'KBCol[2]'
        Info: 2: + IC(6.309 ns) + CELL(0.442 ns) = 8.220 ns; Loc. = LC_X32_Y15_N5; Fanout = 2; COMB Node = 'Mux~528'
        Info: 3: + IC(1.247 ns) + CELL(0.590 ns) = 10.057 ns; Loc. = LC_X31_Y16_N7; Fanout = 1; COMB Node = 'Mux~529'
        Info: 4: + IC(0.431 ns) + CELL(0.738 ns) = 11.226 ns; Loc. = LC_X31_Y16_N1; Fanout = 1; REG Node = 'seg7[6]~reg0'
        Info: Total cell delay = 3.239 ns ( 28.85 % )
        Info: Total interconnect delay = 7.987 ns ( 71.15 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.962 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y16_N1; Fanout = 1; REG Node = 'seg7[6]~reg0'
        Info: Total cell delay = 2.180 ns ( 73.60 % )
        Info: Total interconnect delay = 0.782 ns ( 26.40 % )
Info: tco from clock "clk" to destination pin "seg7[5]" through register "seg7[5]~reg0" is 7.330 ns
    Info: + Longest clock path from clock "clk" to source register is 2.962 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y16_N9; Fanout = 1; REG Node = 'seg7[5]~reg0'
        Info: Total cell delay = 2.180 ns ( 73.60 % )
        Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.144 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y16_N9; Fanout = 1; REG Node = 'seg7[5]~reg0'
        Info: 2: + IC(2.036 ns) + CELL(2.108 ns) = 4.144 ns; Loc. = PIN_183; Fanout = 0; PIN Node = 'seg7[5]'
        Info: Total cell delay = 2.108 ns ( 50.87 % )
        Info: Total interconnect delay = 2.036 ns ( 49.13 % )
Info: th for register "seg7[0]~reg0" (data pin = "KBCol[2]", clock pin = "clk") is -5.695 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.962 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X32_Y16_N4; Fanout = 1; REG Node = 'seg7[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 73.60 % )
        Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 8.672 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_134; Fanout = 11; PIN Node = 'KBCol[2]'
        Info: 2: + IC(6.349 ns) + CELL(0.114 ns) = 7.932 ns; Loc. = LC_X32_Y16_N0; Fanout = 4; COMB Node = 'Mux~527'
        Info: 3: + IC(0.431 ns) + CELL(0.309 ns) = 8.672 ns; Loc. = LC_X32_Y16_N4; Fanout = 1; REG Node = 'seg7[0]~reg0'
        Info: Total cell delay = 1.892 ns ( 21.82 % )
        Info: Total interconnect delay = 6.780 ns ( 78.18 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu May 01 11:54:14 2008
    Info: Elapsed time: 00:00:01