📄 jianpan.tan.rpt
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Timing Analyzer report for jianpan
Thu May 01 11:54:14 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 8.301 ns ; KBCol[2] ; seg7[6]~reg0 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 7.330 ns ; seg7[5]~reg0 ; seg7[5] ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -5.695 ns ; KBCol[2] ; seg7[0]~reg0 ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; sta[1] ; seg7[1]~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; sta[1] ; seg7[1]~reg0 ; clk ; clk ; None ; None ; 2.861 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; sta[1] ; seg7[3]~reg0 ; clk ; clk ; None ; None ; 2.685 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; seg7[2]~reg0 ; clk ; clk ; None ; None ; 2.660 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; sta[1] ; seg7[4]~reg0 ; clk ; clk ; None ; None ; 2.621 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; sta[1] ; seg7[0]~reg0 ; clk ; clk ; None ; None ; 2.617 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; KBRow[1]~reg0 ; clk ; clk ; None ; None ; 2.513 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; KBRow[3]~reg0 ; clk ; clk ; None ; None ; 2.512 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; KBRow[0]~reg0 ; clk ; clk ; None ; None ; 2.508 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[1] ; clk ; clk ; None ; None ; 2.506 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; KBRow[2]~reg0 ; clk ; clk ; None ; None ; 2.504 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; seg7[6]~reg0 ; clk ; clk ; None ; None ; 2.497 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; seg7[1]~reg0 ; clk ; clk ; None ; None ; 2.493 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; seg7[3]~reg0 ; clk ; clk ; None ; None ; 2.334 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; sta[1] ; seg7[5]~reg0 ; clk ; clk ; None ; None ; 2.174 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; sta[1] ; seg7[2]~reg0 ; clk ; clk ; None ; None ; 2.173 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; seg7[0]~reg0 ; clk ; clk ; None ; None ; 2.040 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; seg7[4]~reg0 ; clk ; clk ; None ; None ; 2.040 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; sta[1] ; clk ; clk ; None ; None ; 2.038 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; sta[1] ; seg7[6]~reg0 ; clk ; clk ; None ; None ; 1.881 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; seg7[5]~reg0 ; clk ; clk ; None ; None ; 1.453 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[0] ; count[0] ; clk ; clk ; None ; None ; 1.036 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; KBRow[3]~reg0 ; clk ; clk ; None ; None ; 0.898 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; KBRow[1]~reg0 ; clk ; clk ; None ; None ; 0.897 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; KBRow[0]~reg0 ; clk ; clk ; None ; None ; 0.892 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; KBRow[2]~reg0 ; clk ; clk ; None ; None ; 0.891 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; count[1] ; count[1] ; clk ; clk ; None ; None ; 0.888 ns ;
+-------+------------------------------------------------+----------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+----------+--------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+----------+--------------+----------+
; N/A ; None ; 8.301 ns ; KBCol[2] ; seg7[6]~reg0 ; clk ;
; N/A ; None ; 8.296 ns ; KBCol[0] ; seg7[6]~reg0 ; clk ;
; N/A ; None ; 8.267 ns ; KBCol[3] ; seg7[6]~reg0 ; clk ;
; N/A ; None ; 8.235 ns ; KBCol[0] ; seg7[1]~reg0 ; clk ;
; N/A ; None ; 8.230 ns ; KBCol[2] ; seg7[1]~reg0 ; clk ;
; N/A ; None ; 8.220 ns ; KBCol[3] ; seg7[1]~reg0 ; clk ;
; N/A ; None ; 8.185 ns ; KBCol[1] ; seg7[6]~reg0 ; clk ;
; N/A ; None ; 8.131 ns ; KBCol[1] ; seg7[1]~reg0 ; clk ;
; N/A ; None ; 8.097 ns ; KBCol[2] ; seg7[3]~reg0 ; clk ;
; N/A ; None ; 8.095 ns ; KBCol[0] ; seg7[3]~reg0 ; clk ;
; N/A ; None ; 8.073 ns ; KBCol[3] ; seg7[3]~reg0 ; clk ;
; N/A ; None ; 7.995 ns ; KBCol[0] ; seg7[4]~reg0 ; clk ;
; N/A ; None ; 7.991 ns ; KBCol[0] ; seg7[0]~reg0 ; clk ;
; N/A ; None ; 7.990 ns ; KBCol[2] ; seg7[4]~reg0 ; clk ;
; N/A ; None ; 7.988 ns ; KBCol[1] ; seg7[3]~reg0 ; clk ;
; N/A ; None ; 7.986 ns ; KBCol[2] ; seg7[0]~reg0 ; clk ;
; N/A ; None ; 7.980 ns ; KBCol[3] ; seg7[4]~reg0 ; clk ;
; N/A ; None ; 7.976 ns ; KBCol[3] ; seg7[0]~reg0 ; clk ;
; N/A ; None ; 7.891 ns ; KBCol[1] ; seg7[4]~reg0 ; clk ;
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