mul8x8.v

来自「ARM7_verilog代码」· Verilog 代码 · 共 15 行

module mul8X8(clk,rst,en,a,b,c);
  input clk,rst,en;
  wire clk,rst;
  input [7:0]a,b;
  wire [7:0]a,b;
  output [15:0]c;
  reg [15:0]c;

  always @(posedge clk)
    if(~rst)
      c<=16'b0;
    else  c<=a*b;

endmodule