booth_mul.v

来自「ARM7_verilog代码」· Verilog 代码 · 共 62 行

//---------------------------------------
// Lib  : boothmul
// Unit : Booth_Mul
//---------------------------------------

module Booth_Mul(M, Q, contrl, Ready, A);
  input [31:0] M;
  input [31:0] Q;
  input contrl;
  output Ready;
  output [31:0] A;
  reg Ready;
  reg M;
  reg Q;
  reg [31:0] A;

  task proc_shift_right;
  begin : S0
    P <= Q(0);
    temp <= A(0);
    for i<=0 to 30;
       A(i+1)<=A(i);
    end
    if (A(30) ==1) begin 
       A(31) <= 1;
    end
    else begin 
      A(31) <= 0;
    end
  endtask

  task proc_Booth_Mul_D0;
  begin
    if (Q(0)==1 && P ==0;) begin
      A(31,0)<=A(31,0)-M(31,0);
    end
    else begin
      if (Q(0)==0 && P==1;) begin
        A(31,0) <= A(31,0) + M(31,0);

      end
    end
    proc_shift_right;
    N <= N-1;
    if (!(N == 0;
    )) begin
      proc_Booth_Mul_D0;
    end
  end
  endtask

  always @(M or Q or contrl)
  begin : S0
    A <= 0;
    P <= 0;
    N <= 32;
    proc_Booth_Mul_D0;
  end

endmodule