simple_byte_pipe.v

将msp430与使用nios的fpga相连

module simple_byte_pipe (
              clk,
              reset_n,
              readdata,
              read_waitrequest,

              write_waitrequest,

              read_address,
              read,

              write_address,
              write,
              writedata
           )
;

  input            clk;
  input            reset_n;

  output [4:0] read_address;
  output [4:0] write_address;

  output           read;
  output           write;
  output  [  7: 0] writedata;
  input   [  7: 0] readdata;
  input            read_waitrequest;
  input            write_waitrequest;

  assign read = 1'b1;

  reg [7:0] writedata;
  reg write;

  always @(posedge clk or negedge reset_n) begin
    if (~reset_n) begin
      write <= 1'b0;
      writedata <= 8'b00000000;
    end
    else begin
      if (~read_waitrequest) begin
        write <= 1'b1;
        writedata <= readdata;
      end
      if (read_waitrequest && ~write_waitrequest) begin
        write <= 1'b0;
      end
    end
  end

  assign read_address = 5'b00000;
  assign write_address = 5'b00000;

endmodule