class.ptf

将msp430与使用nios的fpga相连

#
# This class.ptf file built by Component Editor
# 2007.09.22.14:14:11
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
# interfere with Component Editor's ability to
# read and edit it. And then Component Editor
# will overwrite your changes anyway. So, for
# the very best results, just relax and
# DO NOT MODIFY THIS FILE
#
CLASS simple_byte_pipe
{
   CB_GENERATOR 
   {
      HDL_FILES 
      {
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "verilog";
            filepath = "hdl/simple_byte_pipe.v";
         }
      }
      top_module_name = "simple_byte_pipe.v:simple_byte_pipe";
      emit_system_h = "1";
      LIBRARIES 
      {
      }
   }
   MODULE_DEFAULTS global_signals
   {
      class = "simple_byte_pipe";
      class_version = "1.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Has_Clock = "1";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      COMPONENT_BUILDER 
      {
         GLS_SETTINGS 
         {
         }
      }
      PORT_WIRING 
      {
         PORT clk
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "clk";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT reset_n
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "reset_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         hdl_parameters 
         {
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
         }
      }
      MASTER r
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "1";
            Has_Clock = "0";
            Address_Width = "5";
            Data_Width = "8";
            Do_Stream_Reads = "1";
            Do_Stream_Writes = "0";
            Is_Asynchronous = "0";
            Has_IRQ = "0";
            Irq_Scheme = "none";
            Interrupt_Range = "";
            Is_Readable = "1";
            Is_Writable = "0";
            Is_Big_Endian = "0";
            Register_Outgoing_Signals = "0";
         }
         COMPONENT_BUILDER 
         {
            AVM_SETTINGS 
            {
               stream_reads = "1";
               stream_writes = "0";
               irq_width = "0";
               irq_number_width = "0";
               irq_scheme = "none";
               Is_Asynchronous = "0";
               Is_Big_Endian = "0";
            }
         }
         PORT_WIRING 
         {
            PORT readdata
            {
               width = "8";
               width_expression = "";
               direction = "input";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT read_address
            {
               width = "5";
               width_expression = "";
               direction = "output";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT read
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "read";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT read_waitrequest
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "waitrequest";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
      MASTER w
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "2";
            Has_Clock = "0";
            Address_Width = "5";
            Data_Width = "8";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "1";
            Is_Asynchronous = "0";
            Has_IRQ = "0";
            Irq_Scheme = "none";
            Interrupt_Range = "";
            Is_Readable = "0";
            Is_Writable = "1";
            Is_Big_Endian = "0";
            Register_Outgoing_Signals = "0";
         }
         COMPONENT_BUILDER 
         {
            AVM_SETTINGS 
            {
               stream_reads = "0";
               stream_writes = "1";
               irq_width = "0";
               irq_number_width = "0";
               irq_scheme = "none";
               Is_Asynchronous = "0";
               Is_Big_Endian = "0";
            }
         }
         PORT_WIRING 
         {
            PORT write_address
            {
               width = "5";
               width_expression = "";
               direction = "output";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT write
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "write";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT writedata
            {
               width = "8";
               width_expression = "";
               direction = "output";
               type = "writedata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT write_waitrequest
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "waitrequest";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "simple_byte_pipe";
         technology = "Plumbing";
      }
      WIZARD_UI the_wizard_ui
      {
         title = "simple_byte_pipe - {{ $MOD }}";
         CONTEXT 
         {
            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_global_signals = "SYSTEM_BUILDER_INFO";
            SBI_r = "MASTER r/SYSTEM_BUILDER_INFO";
            SBI_w = "MASTER w/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "<b>simple_byte_pipe 1.0</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2007.09.22.14:14:11";
               }
               TEXT 
               {
                  title = "Class name: simple_byte_pipe";
               }
               TEXT 
               {
                  title = "Class version: 1.0";
               }
               TEXT 
               {
                  title = "Component name: simple_byte_pipe";
               }
               TEXT 
               {
                  title = "Component Group: Plumbing";
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "7.10";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
      }
      SW_FILES 
      {
      }
      built_on = "2007.09.22.14:14:11";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE simple_byte_pipe.v
         {
            file_mod = "Sat Sep 22 13:24:10 PDT 2007";
            quartus_map_start = "Sat Sep 22 14:12:15 PDT 2007";
            quartus_map_finished = "Sat Sep 22 14:12:19 PDT 2007";
            #found 1 valid modules
            WRAPPER simple_byte_pipe
            {
               CLASS simple_byte_pipe
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           type = "";
                           filepath = "C:/temp/tb_8a/simple_byte_pipe.v";
                        }
                     }
                     top_module_name = "simple_byte_pipe";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "simple_byte_pipe";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT readdata
                           {
                              width = "8";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT read_address
                           {
                              width = "5";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT read
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT write_address
                           {
                              width = "5";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT write
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT writedata
                           {
                              width = "8";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     SLAVE waitrequest
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT read_waitrequest
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "read";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT write_waitrequest
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "write";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     PORT_WIRING 
                     {
                        PORT clk
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "clk";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                        PORT reset_n
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "reset_n";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "simple_byte_pipe";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
               }
            }
         }
      }
   }
   ASSOCIATED_FILES 
   {
      Add_Program = "the_wizard_ui";
      Edit_Program = "the_wizard_ui";
      Generator_Program = "cb_generator.pl";
   }
}