dummy.v

来自「将msp430与使用nios的fpga相连」· Verilog 代码 · 共 31 行

module dummy(
  clk,
  reset_n,
  address,
  read,
  readdata,
  write,
  byteenable,
  writedata,
  waitrequest
);
  input clk;
  input reset_n;
  input [31:0] readdata;
  input waitrequest;

  output [31:0] address;
  output read;
  output write;
  output [31:0] writedata;
  output [3:0] byteenable;
  
  assign read = 1'b0;
  assign write = 1'b0;
  assign writedata = 32'b0;
  assign address = 32'b0;
  assign byteenable = 4'b0;

endmodule