reg_counter.edf

程序补充说明：时钟输入：在每个时钟的正沿或负沿对数据进行处理。时钟的正沿有效还是负沿有效

(edif reg_counter
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2006 1 10 1 15 34)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "8.1.0, Build 540R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell LUT3_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT2_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT1_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell BUFGP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDR (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port R (direction INPUT))
         )
       )
    )
    (cell FDC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell reg_counter (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port (array (rename cnt_reg_s "cnt_reg_s[3:0]") 4) (direction OUTPUT))
           (port (array (rename cnt_reg_a "cnt_reg_a[3:0]") 4) (direction OUTPUT))
           (port clock (direction INPUT)
 )
           (port reset_ (direction INPUT)
 )
         )
         (contents
          (instance (rename cnt_reg_sZ0Z_0 "cnt_reg_s[0]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename cnt_reg_sZ0Z_1 "cnt_reg_s[1]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename cnt_reg_sZ0Z_2 "cnt_reg_s[2]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename cnt_reg_sZ0Z_3 "cnt_reg_s[3]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance reset__c_i (viewRef PRIM (cellRef INV (libraryRef UNILIB)))          )
          (instance un3_cnt_reg_a_axbxc0 (viewRef PRIM (cellRef LUT1_L (libraryRef VIRTEX)))
           (property init (string "1"))
          )
          (instance un3_cnt_reg_a_axbxc1 (viewRef PRIM (cellRef LUT2_L (libraryRef VIRTEX)))
           (property init (string "6"))
          )
          (instance un3_cnt_reg_a_axbxc2 (viewRef PRIM (cellRef LUT3_L (libraryRef VIRTEX)))
           (property init (string "78"))
          )
          (instance (rename cnt_reg_a_c_i_3 "cnt_reg_a_c_i[3]") (viewRef PRIM (cellRef LUT1_L (libraryRef VIRTEX)))
           (property init (string "1"))
          )
          (instance un3_cnt_reg_s_axbxc0 (viewRef PRIM (cellRef LUT1_L (libraryRef VIRTEX)))
           (property init (string "1"))
          )
          (instance un3_cnt_reg_s_axbxc1 (viewRef PRIM (cellRef LUT2_L (libraryRef VIRTEX)))
           (property init (string "6"))
          )
          (instance un3_cnt_reg_s_axbxc2 (viewRef PRIM (cellRef LUT3_L (libraryRef VIRTEX)))
           (property init (string "78"))
          )
          (instance (rename cnt_reg_s_c_i_3 "cnt_reg_s_c_i[3]") (viewRef PRIM (cellRef LUT1_L (libraryRef VIRTEX)))
           (property init (string "1"))
          )
          (instance clock_ibuf (viewRef PRIM (cellRef BUFGP (libraryRef VIRTEX)))
          )
          (instance (rename cnt_reg_a_obuf_3 "cnt_reg_a_obuf[3]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename cnt_reg_a_obuf_2 "cnt_reg_a_obuf[2]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename cnt_reg_a_obuf_1 "cnt_reg_a_obuf[1]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename cnt_reg_a_obuf_0 "cnt_reg_a_obuf[0]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename cnt_reg_s_obuf_3 "cnt_reg_s_obuf[3]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename cnt_reg_s_obuf_2 "cnt_reg_s_obuf[2]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename cnt_reg_s_obuf_1 "cnt_reg_s_obuf[1]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename cnt_reg_s_obuf_0 "cnt_reg_s_obuf[0]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance reset__ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename cnt_reg_aZ0Z_3 "cnt_reg_a[3]") (viewRef PRIM (cellRef FDR (libraryRef UNILIB)))
          )
          (instance (rename cnt_reg_aZ0Z_2 "cnt_reg_a[2]") (viewRef PRIM (cellRef FDR (libraryRef UNILIB)))
          )
          (instance (rename cnt_reg_aZ0Z_1 "cnt_reg_a[1]") (viewRef PRIM (cellRef FDR (libraryRef UNILIB)))
          )
          (instance (rename cnt_reg_aZ0Z_0 "cnt_reg_a[0]") (viewRef PRIM (cellRef FDR (libraryRef UNILIB)))
          )
          (net clock (joined
           (portRef clock)
           (portRef I (instanceRef clock_ibuf))
          ))
          (net reset_ (joined
           (portRef reset_)
           (portRef I (instanceRef reset__ibuf))
          ))
          (net (rename cnt_reg_s_0 "cnt_reg_s[0]") (joined
           (portRef O (instanceRef cnt_reg_s_obuf_0))
           (portRef (member cnt_reg_s 3))
          ))
          (net (rename cnt_reg_s_1 "cnt_reg_s[1]") (joined
           (portRef O (instanceRef cnt_reg_s_obuf_1))
           (portRef (member cnt_reg_s 2))
          ))
          (net (rename cnt_reg_s_2 "cnt_reg_s[2]") (joined
           (portRef O (instanceRef cnt_reg_s_obuf_2))
           (portRef (member cnt_reg_s 1))
          ))
          (net (rename cnt_reg_s_3 "cnt_reg_s[3]") (joined
           (portRef O (instanceRef cnt_reg_s_obuf_3))
           (portRef (member cnt_reg_s 0))
          ))
          (net (rename cnt_reg_a_0 "cnt_reg_a[0]") (joined
           (portRef O (instanceRef cnt_reg_a_obuf_0))
           (portRef (member cnt_reg_a 3))
          ))
          (net (rename cnt_reg_a_1 "cnt_reg_a[1]") (joined
           (portRef O (instanceRef cnt_reg_a_obuf_1))
           (portRef (member cnt_reg_a 2))
          ))
          (net (rename cnt_reg_a_2 "cnt_reg_a[2]") (joined
           (portRef O (instanceRef cnt_reg_a_obuf_2))
           (portRef (member cnt_reg_a 1))
          ))
          (net (rename cnt_reg_a_3 "cnt_reg_a[3]") (joined
           (portRef O (instanceRef cnt_reg_a_obuf_3))
           (portRef (member cnt_reg_a 0))
          ))
          (net clock_c (joined
           (portRef O (instanceRef clock_ibuf))
           (portRef C (instanceRef cnt_reg_aZ0Z_0))
           (portRef C (instanceRef cnt_reg_aZ0Z_1))
           (portRef C (instanceRef cnt_reg_aZ0Z_2))
           (portRef C (instanceRef cnt_reg_aZ0Z_3))
           (portRef C (instanceRef cnt_reg_sZ0Z_3))
           (portRef C (instanceRef cnt_reg_sZ0Z_2))
           (portRef C (instanceRef cnt_reg_sZ0Z_1))
           (portRef C (instanceRef cnt_reg_sZ0Z_0))
          ))
          (net (rename cnt_reg_s_c_0 "cnt_reg_s_c[0]") (joined
           (portRef Q (instanceRef cnt_reg_sZ0Z_0))
           (portRef I (instanceRef cnt_reg_s_obuf_0))
           (portRef I0 (instanceRef un3_cnt_reg_s_axbxc2))
           (portRef I0 (instanceRef un3_cnt_reg_s_axbxc1))
           (portRef I0 (instanceRef un3_cnt_reg_s_axbxc0))
          ))
          (net (rename un3_cnt_reg_s_axbxcZ0Z0 "un3_cnt_reg_s_axbxc0") (joined
           (portRef LO (instanceRef un3_cnt_reg_s_axbxc0))
           (portRef D (instanceRef cnt_reg_sZ0Z_0))
          ))
          (net (rename reset__c_iZ0 "reset__c_i") (joined
           (portRef O (instanceRef reset__c_i))
           (portRef R (instanceRef cnt_reg_aZ0Z_0))
           (portRef R (instanceRef cnt_reg_aZ0Z_1))
           (portRef R (instanceRef cnt_reg_aZ0Z_2))
           (portRef R (instanceRef cnt_reg_aZ0Z_3))
           (portRef CLR (instanceRef cnt_reg_sZ0Z_3))
           (portRef CLR (instanceRef cnt_reg_sZ0Z_2))
           (portRef CLR (instanceRef cnt_reg_sZ0Z_1))
           (portRef CLR (instanceRef cnt_reg_sZ0Z_0))
          ))
          (net (rename cnt_reg_s_c_1 "cnt_reg_s_c[1]") (joined
           (portRef Q (instanceRef cnt_reg_sZ0Z_1))
           (portRef I (instanceRef cnt_reg_s_obuf_1))
           (portRef I1 (instanceRef un3_cnt_reg_s_axbxc2))
           (portRef I1 (instanceRef un3_cnt_reg_s_axbxc1))
          ))
          (net (rename un3_cnt_reg_s_axbxcZ0Z1 "un3_cnt_reg_s_axbxc1") (joined
           (portRef LO (instanceRef un3_cnt_reg_s_axbxc1))
           (portRef D (instanceRef cnt_reg_sZ0Z_1))
          ))
          (net (rename cnt_reg_s_c_2 "cnt_reg_s_c[2]") (joined
           (portRef Q (instanceRef cnt_reg_sZ0Z_2))
           (portRef I (instanceRef cnt_reg_s_obuf_2))
           (portRef I2 (instanceRef un3_cnt_reg_s_axbxc2))
          ))
          (net (rename un3_cnt_reg_s_axbxcZ0Z2 "un3_cnt_reg_s_axbxc2") (joined
           (portRef LO (instanceRef un3_cnt_reg_s_axbxc2))
           (portRef D (instanceRef cnt_reg_sZ0Z_2))
          ))
          (net (rename cnt_reg_s_c_3 "cnt_reg_s_c[3]") (joined
           (portRef Q (instanceRef cnt_reg_sZ0Z_3))
           (portRef I (instanceRef cnt_reg_s_obuf_3))
           (portRef I0 (instanceRef cnt_reg_s_c_i_3))
          ))
          (net (rename cnt_reg_s_c_iZ0Z_3 "cnt_reg_s_c_i[3]") (joined
           (portRef LO (instanceRef cnt_reg_s_c_i_3))
           (portRef D (instanceRef cnt_reg_sZ0Z_3))
          ))
          (net reset__c (joined
           (portRef O (instanceRef reset__ibuf))
           (portRef I (instanceRef reset__c_i))
          ))
          (net (rename cnt_reg_a_c_0 "cnt_reg_a_c[0]") (joined
           (portRef Q (instanceRef cnt_reg_aZ0Z_0))
           (portRef I (instanceRef cnt_reg_a_obuf_0))
           (portRef I0 (instanceRef un3_cnt_reg_a_axbxc2))
           (portRef I0 (instanceRef un3_cnt_reg_a_axbxc1))
           (portRef I0 (instanceRef un3_cnt_reg_a_axbxc0))
          ))
          (net (rename un3_cnt_reg_a_axbxcZ0Z0 "un3_cnt_reg_a_axbxc0") (joined
           (portRef LO (instanceRef un3_cnt_reg_a_axbxc0))
           (portRef D (instanceRef cnt_reg_aZ0Z_0))
          ))
          (net (rename cnt_reg_a_c_1 "cnt_reg_a_c[1]") (joined
           (portRef Q (instanceRef cnt_reg_aZ0Z_1))
           (portRef I (instanceRef cnt_reg_a_obuf_1))
           (portRef I1 (instanceRef un3_cnt_reg_a_axbxc2))
           (portRef I1 (instanceRef un3_cnt_reg_a_axbxc1))
          ))
          (net (rename un3_cnt_reg_a_axbxcZ0Z1 "un3_cnt_reg_a_axbxc1") (joined
           (portRef LO (instanceRef un3_cnt_reg_a_axbxc1))
           (portRef D (instanceRef cnt_reg_aZ0Z_1))
          ))
          (net (rename cnt_reg_a_c_2 "cnt_reg_a_c[2]") (joined
           (portRef Q (instanceRef cnt_reg_aZ0Z_2))
           (portRef I (instanceRef cnt_reg_a_obuf_2))
           (portRef I2 (instanceRef un3_cnt_reg_a_axbxc2))
          ))
          (net (rename un3_cnt_reg_a_axbxcZ0Z2 "un3_cnt_reg_a_axbxc2") (joined
           (portRef LO (instanceRef un3_cnt_reg_a_axbxc2))
           (portRef D (instanceRef cnt_reg_aZ0Z_2))
          ))
          (net (rename cnt_reg_a_c_3 "cnt_reg_a_c[3]") (joined
           (portRef Q (instanceRef cnt_reg_aZ0Z_3))
           (portRef I (instanceRef cnt_reg_a_obuf_3))
           (portRef I0 (instanceRef cnt_reg_a_c_i_3))
          ))
          (net (rename cnt_reg_a_c_iZ0Z_3 "cnt_reg_a_c_i[3]") (joined
           (portRef LO (instanceRef cnt_reg_a_c_i_3))
           (portRef D (instanceRef cnt_reg_aZ0Z_3))
          ))
         )
       )
    )
  )
  (design reg_counter (cellRef reg_counter (libraryRef work))
	(property PART (string "xc3s100evq100-4") (owner "Xilinx")))
)