reg_counter.prj

程序补充说明：时钟输入：在每个时钟的正沿或负沿对数据进行处理。时钟的正沿有效还是负沿有效

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\Example-4-1\reg_counter.prj
#-- Written on Tue Jan 10 01:15:09 2006


#add_file options
add_file -verilog "C:/prj/Example-4-1/reg_counter.v"


#implementation: "rev_2"
impl -add rev_2

#device options
set_option -technology SPARTAN3E
set_option -part XC3S100E
set_option -package VQ100
set_option -speed_grade -4

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 0
set_option -use_fsm_explorer 0

#map options
set_option -frequency 100.000
set_option -run_prop_extract 0
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -fixgatedclocks 0
set_option -retiming 0
set_option -modular 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -no_sequential_opt 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_2/reg_counter.edf"

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1

#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0
impl -active "rev_2"