moore2.tan.rpt

moore状态机,综合已通过

; N/A   ; None         ; 3.851 ns   ; DATAIN[1] ; current_state.st2 ; CLK      ;
; N/A   ; None         ; 3.851 ns   ; DATAIN[1] ; current_state.st1 ; CLK      ;
; N/A   ; None         ; 3.850 ns   ; DATAIN[1] ; current_state.st0 ; CLK      ;
; N/A   ; None         ; 3.849 ns   ; DATAIN[1] ; current_state.st3 ; CLK      ;
; N/A   ; None         ; 3.848 ns   ; DATAIN[1] ; current_state.st4 ; CLK      ;
+-------+--------------+------------+-----------+-------------------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+-------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To   ; From Clock ;
+-------+--------------+------------+-------------------+------+------------+
; N/A   ; None         ; 8.111 ns   ; current_state.st2 ; Q[0] ; CLK        ;
; N/A   ; None         ; 7.887 ns   ; current_state.st2 ; Q[2] ; CLK        ;
; N/A   ; None         ; 7.822 ns   ; current_state.st3 ; Q[0] ; CLK        ;
; N/A   ; None         ; 7.594 ns   ; current_state.st3 ; Q[3] ; CLK        ;
; N/A   ; None         ; 7.411 ns   ; current_state.st1 ; Q[2] ; CLK        ;
; N/A   ; None         ; 7.408 ns   ; current_state.st1 ; Q[3] ; CLK        ;
; N/A   ; None         ; 6.833 ns   ; current_state.st3 ; Q[1] ; CLK        ;
+-------+--------------+------------+-------------------+------+------------+


+------------------------------------------------------------------------------------+
; th                                                                                 ;
+---------------+-------------+-----------+-----------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To                ; To Clock ;
+---------------+-------------+-----------+-----------+-------------------+----------+
; N/A           ; None        ; -3.796 ns ; DATAIN[1] ; current_state.st4 ; CLK      ;
; N/A           ; None        ; -3.797 ns ; DATAIN[1] ; current_state.st3 ; CLK      ;
; N/A           ; None        ; -3.798 ns ; DATAIN[1] ; current_state.st0 ; CLK      ;
; N/A           ; None        ; -3.799 ns ; DATAIN[1] ; current_state.st2 ; CLK      ;
; N/A           ; None        ; -3.799 ns ; DATAIN[1] ; current_state.st1 ; CLK      ;
; N/A           ; None        ; -3.957 ns ; DATAIN[0] ; current_state.st2 ; CLK      ;
; N/A           ; None        ; -3.957 ns ; DATAIN[0] ; current_state.st0 ; CLK      ;
; N/A           ; None        ; -3.958 ns ; DATAIN[0] ; current_state.st1 ; CLK      ;
; N/A           ; None        ; -3.958 ns ; DATAIN[0] ; current_state.st4 ; CLK      ;
; N/A           ; None        ; -3.959 ns ; DATAIN[0] ; current_state.st3 ; CLK      ;
+---------------+-------------+-----------+-----------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun May 18 00:11:03 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MOORE2 -c MOORE2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "current_state.st4" and destination register "current_state.st4"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.106 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y6_N8; Fanout = 2; REG Node = 'current_state.st4'
            Info: 2: + IC(0.797 ns) + CELL(0.309 ns) = 1.106 ns; Loc. = LC_X1_Y6_N8; Fanout = 2; REG Node = 'current_state.st4'
            Info: Total cell delay = 0.309 ns ( 27.94 % )
            Info: Total interconnect delay = 0.797 ns ( 72.06 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.903 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y6_N8; Fanout = 2; REG Node = 'current_state.st4'
                Info: Total cell delay = 2.180 ns ( 75.09 % )
                Info: Total interconnect delay = 0.723 ns ( 24.91 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.903 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y6_N8; Fanout = 2; REG Node = 'current_state.st4'
                Info: Total cell delay = 2.180 ns ( 75.09 % )
                Info: Total interconnect delay = 0.723 ns ( 24.91 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "current_state.st3" (data pin = "DATAIN[0]", clock pin = "CLK") is 4.011 ns
    Info: + Longest pin to register delay is 6.877 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_45; Fanout = 5; PIN Node = 'DATAIN[0]'
        Info: 2: + IC(4.670 ns) + CELL(0.738 ns) = 6.877 ns; Loc. = LC_X1_Y6_N9; Fanout = 5; REG Node = 'current_state.st3'
        Info: Total cell delay = 2.207 ns ( 32.09 % )
        Info: Total interconnect delay = 4.670 ns ( 67.91 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y6_N9; Fanout = 5; REG Node = 'current_state.st3'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: tco from clock "CLK" to destination pin "Q[0]" through register "current_state.st2" is 8.111 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y6_N6; Fanout = 4; REG Node = 'current_state.st2'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.984 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y6_N6; Fanout = 4; REG Node = 'current_state.st2'
        Info: 2: + IC(0.569 ns) + CELL(0.590 ns) = 1.159 ns; Loc. = LC_X1_Y6_N3; Fanout = 1; COMB Node = 'Q~2'
        Info: 3: + IC(1.717 ns) + CELL(2.108 ns) = 4.984 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'Q[0]'
        Info: Total cell delay = 2.698 ns ( 54.13 % )
        Info: Total interconnect delay = 2.286 ns ( 45.87 % )
Info: th for register "current_state.st4" (data pin = "DATAIN[1]", clock pin = "CLK") is -3.796 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.903 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y6_N8; Fanout = 2; REG Node = 'current_state.st4'
        Info: Total cell delay = 2.180 ns ( 75.09 % )
        Info: Total interconnect delay = 0.723 ns ( 24.91 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.714 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_44; Fanout = 5; PIN Node = 'DATAIN[1]'
        Info: 2: + IC(4.638 ns) + CELL(0.607 ns) = 6.714 ns; Loc. = LC_X1_Y6_N8; Fanout = 2; REG Node = 'current_state.st4'
        Info: Total cell delay = 2.076 ns ( 30.92 % )
        Info: Total interconnect delay = 4.638 ns ( 69.08 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun May 18 00:11:03 2008
    Info: Elapsed time: 00:00:00