moore2.tan.qmsg

moore状态机,综合已通过

{ "Info" "ITDB_TSU_RESULT" "current_state.st3 DATAIN\[0\] CLK 4.011 ns register " "Info: tsu for register \"current_state.st3\" (data pin = \"DATAIN\[0\]\", clock pin = \"CLK\") is 4.011 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.877 ns + Longest pin register " "Info: + Longest pin to register delay is 6.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DATAIN\[0\] 1 PIN PIN_45 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_45; Fanout = 5; PIN Node = 'DATAIN\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATAIN[0] } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.670 ns) + CELL(0.738 ns) 6.877 ns current_state.st3 2 REG LC_X1_Y6_N9 5 " "Info: 2: + IC(4.670 ns) + CELL(0.738 ns) = 6.877 ns; Loc. = LC_X1_Y6_N9; Fanout = 5; REG Node = 'current_state.st3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.408 ns" { DATAIN[0] current_state.st3 } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 32.09 % ) " "Info: Total cell delay = 2.207 ns ( 32.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.670 ns ( 67.91 % ) " "Info: Total interconnect delay = 4.670 ns ( 67.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.877 ns" { DATAIN[0] current_state.st3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.877 ns" { DATAIN[0] DATAIN[0]~out0 current_state.st3 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.903 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns current_state.st3 2 REG LC_X1_Y6_N9 5 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y6_N9; Fanout = 5; REG Node = 'current_state.st3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.434 ns" { CLK current_state.st3 } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.09 % ) " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 24.91 % ) " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.903 ns" { CLK current_state.st3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.877 ns" { DATAIN[0] current_state.st3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.877 ns" { DATAIN[0] DATAIN[0]~out0 current_state.st3 } { 0.000ns 0.000ns 4.670ns } { 0.000ns 1.469ns 0.738ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.903 ns" { CLK current_state.st3 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[0\] current_state.st2 8.111 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[0\]\" through register \"current_state.st2\" is 8.111 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.903 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns current_state.st2 2 REG LC_X1_Y6_N6 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y6_N6; Fanout = 4; REG Node = 'current_state.st2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.434 ns" { CLK current_state.st2 } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.09 % ) " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 24.91 % ) " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.903 ns" { CLK current_state.st2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 current_state.st2 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.984 ns + Longest register pin " "Info: + Longest register to pin delay is 4.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st2 1 REG LC_X1_Y6_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y6_N6; Fanout = 4; REG Node = 'current_state.st2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { current_state.st2 } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.569 ns) + CELL(0.590 ns) 1.159 ns Q~2 2 COMB LC_X1_Y6_N3 1 " "Info: 2: + IC(0.569 ns) + CELL(0.590 ns) = 1.159 ns; Loc. = LC_X1_Y6_N3; Fanout = 1; COMB Node = 'Q~2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.159 ns" { current_state.st2 Q~2 } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.717 ns) + CELL(2.108 ns) 4.984 ns Q\[0\] 3 PIN PIN_63 0 " "Info: 3: + IC(1.717 ns) + CELL(2.108 ns) = 4.984 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'Q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.825 ns" { Q~2 Q[0] } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns ( 54.13 % ) " "Info: Total cell delay = 2.698 ns ( 54.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.286 ns ( 45.87 % ) " "Info: Total interconnect delay = 2.286 ns ( 45.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.984 ns" { current_state.st2 Q~2 Q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.984 ns" { current_state.st2 Q~2 Q[0] } { 0.000ns 0.569ns 1.717ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.903 ns" { CLK current_state.st2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 current_state.st2 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.984 ns" { current_state.st2 Q~2 Q[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.984 ns" { current_state.st2 Q~2 Q[0] } { 0.000ns 0.569ns 1.717ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "current_state.st4 DATAIN\[1\] CLK -3.796 ns register " "Info: th for register \"current_state.st4\" (data pin = \"DATAIN\[1\]\", clock pin = \"CLK\") is -3.796 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.903 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns current_state.st4 2 REG LC_X1_Y6_N8 2 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X1_Y6_N8; Fanout = 2; REG Node = 'current_state.st4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.434 ns" { CLK current_state.st4 } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.09 % ) " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 24.91 % ) " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.903 ns" { CLK current_state.st4 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 current_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.714 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.714 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DATAIN\[1\] 1 PIN PIN_44 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_44; Fanout = 5; PIN Node = 'DATAIN\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATAIN[1] } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.638 ns) + CELL(0.607 ns) 6.714 ns current_state.st4 2 REG LC_X1_Y6_N8 2 " "Info: 2: + IC(4.638 ns) + CELL(0.607 ns) = 6.714 ns; Loc. = LC_X1_Y6_N8; Fanout = 2; REG Node = 'current_state.st4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.245 ns" { DATAIN[1] current_state.st4 } "NODE_NAME" } } { "MOORE2.vhd" "" { Text "D:/quartus/5_1/MOORE2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns ( 30.92 % ) " "Info: Total cell delay = 2.076 ns ( 30.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.638 ns ( 69.08 % ) " "Info: Total interconnect delay = 4.638 ns ( 69.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.714 ns" { DATAIN[1] current_state.st4 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.714 ns" { DATAIN[1] DATAIN[1]~out0 current_state.st4 } { 0.000ns 0.000ns 4.638ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.903 ns" { CLK current_state.st4 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 current_state.st4 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.714 ns" { DATAIN[1] current_state.st4 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.714 ns" { DATAIN[1] DATAIN[1]~out0 current_state.st4 } { 0.000ns 0.000ns 4.638ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 18 00:11:03 2008 " "Info: Processing ended: Sun May 18 00:11:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}