eda.txt

来自「用VHDL编的两位BCD加法器用VHDL编的两位BCD加法器」· 文本 代码 · 共 53 行

--bcd_add.vhd
--BCD adder,using 2 instances of the component adder4par

ENTITY bcd_add IS
   PORT (
          c0  : IN   BIT;
          a, b: IN   BIT_VECTOR(4 downto 1);
          C4  : OUT  BIT;
          sum : OUT  BIT_VECTOR(4 downto 1));
 END bcd_add;

ARCHITECTURE adder OF bcd_add IS
    -- Componces declaration
       COMPONENT add4par
       PORT (
           c0 : IN   BIT;
          a, b: IN   BIT_VECTOR(4 downto 1);
          C4  : OUT  BIT;
          sum : OUT  BIT_VECTOR(4 downto 1));
  END COMPONENT;
  SIGNAL c4_bin  : BIT;
  SIGNAL sum_bin : BIT_VECTOR(4 downto 1);
  SIGNAL a_bcd   : BIT_VECTOR(4 downto 1);
  SIGNAL b_bcd   : BIT_VECTOR(4 downto 1);
  SIGNAL c0_bcd  : BIT;
BEGIN
--Instantiate 4-bit adder (binary sum)
add_bin: add4par
    PORT MAP (c0  => c0,
              a   => a,
              b   => b,
              c4  => c4_bin,
              sum => sum_bin);
--Instantiate 4-bit adder (binary-BCD converter)
converter: adder4par
    PORT MAP (c0  => c0_bcd,
              a   => a_bcd,
              b   => b_bcd,
              sum => sum);
--Connect components
  c0_bcd      <= '0';
  b_bcd       <= sum_bin;
  a_bcd(4)    <= '0';
  a_bcd(3)    <= c4_bin or (sum_bin(4) and sum_bin(3))
              or (sum_bin(4) and sum_bin(2));
  a_bcd(2)    <= c4_bin or (sum_bin(4) and sum_bin(3))
              or (sum_bin(4) and sum_bin(2));
  a_bcd(1)    <='0';
  c4          <= c4_bin or (sum_bin(4) and sum_bin(3))
              or (sum_bin(4) and sum_bin(2));
END adder;