stimulus1.v

用于数据块容错编码校验的芯片的RS编码器设计的测试代码

/******************************************************************/
/*
本测试文件自动生成了256组3字节长度的数据信息，编码器将根据测试文件提供
的控制信号行为描述对这256组数据信息进行编码，输出码字。完成编码以后，测
试文件还将一一解码这些生成的码字，并对比原始数据信息和解码得到的数据信息。
如果发现了两者不相符的情况，测试文件将记录这个错误。测试文件描述如下。
*/




module stimulus1(
CLK, 
RESET,
DATA_VALID_IN,
DATA_IN,
E_D,
ERR,  
DATA_VALID_OUT,
DATA_OUT);



input DATA_VALID_OUT;
input [7:0] DATA_OUT;
output CLK, RESET, E_D, DATA_VALID_IN;
output [7:0] DATA_IN;
output ERR;

reg ERR;
reg [7:0] c4, c3, c2, c1, c0;
reg CLK, RESET, E_D, DATA_VALID_IN;
reg [7:0] DATA_IN;

integer i, j, k;

RS_5_3_CODEC	u0_(
.CLK(CLK),
.RESET(RESET),
.DATA_VALID_IN(DATA_VALID_IN),
.DATA_IN(DATA_IN),
.E_D(E_D),
.DATA_OUT(DATA_OUT),
.DATA_VALID_OUT(DATA_VALID_OUT));


/////////////////////////	CLK SIGNAL	///////////////////////

initial CLK <= 0;
always 
begin
	#50
	CLK <= !CLK;
end


/////////////////////////	RESET SIGNAL	///////////////////////

initial 
begin
	RESET <= 0;
	#500
	RESET <= 1;
end 


/////////////////////////	DATA_VALID_IN & DATA_IN & E_D	///////////////////////

initial 
begin
DATA_VALID_IN<=1;
E_D<=1;
DATA_IN<=0;
ERR<=0;
#1000

for (i = 80; i < 256; i = i+1)
	for (j = 0; j < 256; j = j+1)
		for (k = 0; k < 256; k = k+1)
		begin
			#100
			#100
			#100
			#100
			#100
			#100
			#100
			#100
			#100
			DATA_VALID_IN<=0;
			E_D<=1;
			DATA_IN<=i;
			#100
			DATA_IN<=j;
			#100
			DATA_IN<=k;
			#100
			DATA_IN<=0;
			DATA_VALID_IN<=1;
			#100
			#100
			#100
			#100
			#100
			#100
			#100
			#100
			#100
			#100
			DATA_VALID_IN<=0;
			E_D<=0;
			DATA_IN<=c4;
			#100
			DATA_IN<=c3;
			#100
			DATA_IN<=c2;
			#100
			DATA_IN<=c1;
			#100
			DATA_IN<=c0;
			#100
			DATA_VALID_IN<=1;

			#150
			if (DATA_OUT!=i)	begin ERR<=1; end
			#100
			if (DATA_OUT!=j)	begin ERR<=1; end
			#100
			if (DATA_OUT!=k)	begin ERR<=1; end
			#50
			ERR<=0;
			
		end
end


			
			
			
		

always@(posedge CLK or negedge RESET)

if (!RESET)
begin
c0<=0;
c1<=0;
c2<=0;
c3<=0;
c4<=0;
end
else if (!DATA_VALID_OUT)	
begin
c0<=DATA_OUT;
c1<=c0;
c2<=c1;
c3<=c2;
c4<=c3;
end




/////////////////////



///////////////////////////////////////////////////////////////// DEC 2





	

always
begin
	#1000000000
	$finish;
end
endmodule