counter16_top.syr

本文件包括多路选择器器建模

     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00161 (counter16__n0016)
     FDC_1:D                   0.709          counter16_clk16_out_0
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_0:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_1 (FF)
  Destination:       counter16_clk16_out_1 (FF)
  Source Clock:      counter16_clk16_out_0:Q falling
  Destination Clock: counter16_clk16_out_0:Q falling

  Data Path: counter16_clk16_out_1 to counter16_clk16_out_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_1 (counter16_clk16_out_1)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00181 (counter16__n0018)
     FDC_1:D                   0.709          counter16_clk16_out_1
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_1:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_2 (FF)
  Destination:       counter16_clk16_out_2 (FF)
  Source Clock:      counter16_clk16_out_1:Q falling
  Destination Clock: counter16_clk16_out_1:Q falling

  Data Path: counter16_clk16_out_2 to counter16_clk16_out_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_2 (counter16_clk16_out_2)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00201 (counter16__n0020)
     FDC_1:D                   0.709          counter16_clk16_out_2
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_2:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_3 (FF)
  Destination:       counter16_clk16_out_3 (FF)
  Source Clock:      counter16_clk16_out_2:Q falling
  Destination Clock: counter16_clk16_out_2:Q falling

  Data Path: counter16_clk16_out_3 to counter16_clk16_out_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_3 (counter16_clk16_out_3)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00221 (counter16__n0022)
     FDC_1:D                   0.709          counter16_clk16_out_3
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_3:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_4 (FF)
  Destination:       counter16_clk16_out_4 (FF)
  Source Clock:      counter16_clk16_out_3:Q falling
  Destination Clock: counter16_clk16_out_3:Q falling

  Data Path: counter16_clk16_out_4 to counter16_clk16_out_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_4 (counter16_clk16_out_4)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00241 (counter16__n0024)
     FDC_1:D                   0.709          counter16_clk16_out_4
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_4:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_5 (FF)
  Destination:       counter16_clk16_out_5 (FF)
  Source Clock:      counter16_clk16_out_4:Q falling
  Destination Clock: counter16_clk16_out_4:Q falling

  Data Path: counter16_clk16_out_5 to counter16_clk16_out_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_5 (counter16_clk16_out_5)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00261 (counter16__n0026)
     FDC_1:D                   0.709          counter16_clk16_out_5
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_5:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_6 (FF)
  Destination:       counter16_clk16_out_6 (FF)
  Source Clock:      counter16_clk16_out_5:Q falling
  Destination Clock: counter16_clk16_out_5:Q falling

  Data Path: counter16_clk16_out_6 to counter16_clk16_out_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_6 (counter16_clk16_out_6)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00281 (counter16__n0028)
     FDC_1:D                   0.709          counter16_clk16_out_6
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_6:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_7 (FF)
  Destination:       counter16_clk16_out_7 (FF)
  Source Clock:      counter16_clk16_out_6:Q falling
  Destination Clock: counter16_clk16_out_6:Q falling

  Data Path: counter16_clk16_out_7 to counter16_clk16_out_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_7 (counter16_clk16_out_7)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00301 (counter16__n0030)
     FDC_1:D                   0.709          counter16_clk16_out_7
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_7:Q'
Delay:               3.675ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_8 (FF)
  Destination:       counter16_clk16_out_8 (FF)
  Source Clock:      counter16_clk16_out_7:Q falling
  Destination Clock: counter16_clk16_out_7:Q falling

  Data Path: counter16_clk16_out_8 to counter16_clk16_out_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            3   1.085   1.332  counter16_clk16_out_8 (counter16_clk16_out_8)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00321 (counter16__n0032)
     FDC_1:D                   0.709          counter16_clk16_out_8
    ----------------------------------------
    Total                      3.675ns (2.343ns logic, 1.332ns route)
                                       (63.8% logic, 36.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_8:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_9 (FF)
  Destination:       counter16_clk16_out_9 (FF)
  Source Clock:      counter16_clk16_out_8:Q falling
  Destination Clock: counter16_clk16_out_8:Q falling

  Data Path: counter16_clk16_out_9 to counter16_clk16_out_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_9 (counter16_clk16_out_9)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00341 (counter16__n0034)
     FDC_1:D                   0.709          counter16_clk16_out_9
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_9:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_10 (FF)
  Destination:       counter16_clk16_out_10 (FF)
  Source Clock:      counter16_clk16_out_9:Q falling
  Destination Clock: counter16_clk16_out_9:Q falling

  Data Path: counter16_clk16_out_10 to counter16_clk16_out_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_10 (counter16_clk16_out_10)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00361 (counter16__n0036)
     FDC_1:D                   0.709          counter16_clk16_out_10
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_10:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_11 (FF)
  Destination:       counter16_clk16_out_11 (FF)
  Source Clock:      counter16_clk16_out_10:Q falling
  Destination Clock: counter16_clk16_out_10:Q falling

  Data Path: counter16_clk16_out_11 to counter16_clk16_out_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_11 (counter16_clk16_out_11)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00381 (counter16__n0038)
     FDC_1:D                   0.709          counter16_clk16_out_11
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_11:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_12 (FF)
  Destination:       counter16_clk16_out_12 (FF)
  Source Clock:      counter16_clk16_out_11:Q falling
  Destination Clock: counter16_clk16_out_11:Q falling

  Data Path: counter16_clk16_out_12 to counter16_clk16_out_12
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_12 (counter16_clk16_out_12)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00401 (counter16__n0040)
     FDC_1:D                   0.709          counter16_clk16_out_12
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'counter16_clk16_out_12:Q'
Delay:               3.549ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_13 (FF)
  Destination:       counter16_clk16_out_13 (FF)
  Source Clock:      counter16_clk16_out_12:Q falling
  Destination Clock: counter16_clk16_out_12:Q falling

  Data Path: counter16_clk16_out_13 to counter16_clk16_out_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_13 (counter16_clk16_out_13)
     LUT1_L:I0->LO         1   0.549   0.000  counter16__n00421 (counter16__n0042)
     FDC_1:D                   0.709          counter16_clk16_out_13
    ----------------------------------------
    Total                      3.549ns (2.343ns logic, 1.206ns route)
                                       (66.0% logic, 34.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'counter16_clk16_out_7:Q'
Offset:              7.085ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_8 (FF)
  Destination:       BZ (PAD)
  Source Clock:      counter16_clk16_out_7:Q falling

  Data Path: counter16_clk16_out_8 to BZ
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            3   1.085   1.332  counter16_clk16_out_8 (counter16_clk16_out_8)
     OBUF:I->O                 4.668          BZ_OBUF (BZ)
    ----------------------------------------
    Total                      7.085ns (5.753ns logic, 1.332ns route)
                                       (81.2% logic, 18.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'counter16_clk16_out_14:Q'
Offset:              6.959ns (Levels of Logic = 1)
  Source:            counter16_clk16_out_15 (FF)
  Destination:       L5 (PAD)
  Source Clock:      counter16_clk16_out_14:Q falling

  Data Path: counter16_clk16_out_15 to L5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.085   1.206  counter16_clk16_out_15 (counter16_clk16_out_15)
     OBUF:I->O                 4.668          L5_OBUF (L5)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 3.31 / 5.64 s | Elapsed : 3.00 / 5.00 s
 
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Total memory usage is 57924 kilobytes