fpga_40rs232.syr

本文件包括多路选择器器建模

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fpga_40RS232.ngr
Top Level Output File Name         : fpga_40RS232
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Macro Statistics :
# Registers                        : 16
#      1-bit register              : 9
#      3-bit register              : 3
#      8-bit register              : 2
#      9-bit register              : 2
# Counters                         : 1
#      8-bit up counter            : 1
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1
# Tristates                        : 2
#      8-bit tristate buffer       : 2
# Comparators                      : 1
#      4-bit comparator less       : 1

Cell Usage :
# BELS                             : 115
#      GND                         : 1
#      LUT1                        : 14
#      LUT1_L                      : 2
#      LUT2                        : 28
#      LUT2_L                      : 1
#      LUT3                        : 10
#      LUT3_L                      : 8
#      LUT4                        : 7
#      LUT4_D                      : 2
#      LUT4_L                      : 5
#      MUXCY                       : 18
#      VCC                         : 1
#      XORCY                       : 18
# FlipFlops/Latches                : 64
#      FDC                         : 14
#      FDC_1                       : 3
#      FDCE                        : 10
#      FDCPE                       : 8
#      FDE                         : 17
#      FDPE                        : 12
# Tri-States                       : 16
#      BUFT                        : 16
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 13
#      IBUF                        : 3
#      OBUF                        : 10
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      47  out of   2352     1%  
 Number of Slice Flip Flops:            64  out of   4704     1%  
 Number of 4 input LUTs:                77  out of   4704     1%  
 Number of bonded IOBs:                 13  out of    144     9%  
 Number of TBUFs:                       16  out of   2352     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK1(CLK11:O)                      | NONE(*)(serial_tx_bit_0)| 61    |
CLK                                | BUFGP                  | 3     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 9.417ns (Maximum Frequency: 106.191MHz)
   Minimum input arrival time before clock: 8.117ns
   Maximum output required time after clock: 9.992ns
   Maximum combinational path delay: 12.884ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK11:O'
Delay:               9.417ns (Levels of Logic = 3)
  Source:            serial_tx_count_1 (FF)
  Destination:       serial_tx_bit_0 (FF)
  Source Clock:      CLK11:O rising
  Destination Clock: CLK11:O rising

  Data Path: serial_tx_count_1 to serial_tx_bit_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   1.292   1.340  serial_tx_count_1 (serial_tx_count_1)
     LUT4:I0->O            2   0.653   1.340  serial_Ker20181 (serial_N2020)
     LUT4_D:I1->LO         1   0.653   0.100  serial_tx_shift33 (N2926)
     LUT2:I0->O           13   0.653   2.500  serial__n00161 (serial__n0016)
     FDE:CE                    0.886          serial_tx_buffer_1
    ----------------------------------------
    Total                      9.417ns (4.137ns logic, 5.280ns route)
                                       (43.9% logic, 56.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'CLK'
Delay:               4.298ns (Levels of Logic = 1)
  Source:            div_0 (FF)
  Destination:       div_2 (FF)
  Source Clock:      CLK falling
  Destination Clock: CLK falling

  Data Path: div_0 to div_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            4   1.292   1.600  div_0 (div_0)
     LUT1:I0->O            1   0.653   0.000  div_Madd__n0000__n00061 (div__n0000<0>)
     FDC_1:D                   0.753          div_0
    ----------------------------------------
    Total                      4.298ns (2.698ns logic, 1.600ns route)
                                       (62.8% logic, 37.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK11:O'
Offset:              8.117ns (Levels of Logic = 11)
  Source:            RD (PAD)
  Destination:       serial_sync_count_7 (FF)
  Destination Clock: CLK11:O rising

  Data Path: RD to serial_sync_count_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             7   0.924   1.950  RD_IBUF (RD_IBUF)
     LUT2:I1->O            4   0.653   1.600  serial_sync_reload40 (CHOICE56)
     LUT4_L:I0->LO         1   0.653   0.000  serial_sync_count_inst_lut3_01 (serial_sync_count_inst_lut3_0)
     MUXCY:S->O            1   0.784   0.000  serial_sync_count_inst_cy_13 (serial_sync_count_inst_cy_13)
     MUXCY:CI->O           1   0.050   0.000  serial_sync_count_inst_cy_14 (serial_sync_count_inst_cy_14)
     MUXCY:CI->O           1   0.050   0.000  serial_sync_count_inst_cy_15 (serial_sync_count_inst_cy_15)
     MUXCY:CI->O           1   0.050   0.000  serial_sync_count_inst_cy_16 (serial_sync_count_inst_cy_16)
     MUXCY:CI->O           1   0.050   0.000  serial_sync_count_inst_cy_17 (serial_sync_count_inst_cy_17)
     MUXCY:CI->O           1   0.050   0.000  serial_sync_count_inst_cy_18 (serial_sync_count_inst_cy_18)
     MUXCY:CI->O           0   0.050   0.000  serial_sync_count_inst_cy_19 (serial_sync_count_inst_cy_19)
     XORCY:CI->O           1   0.500   0.000  serial_sync_count_inst_sum_19 (serial_sync_count_inst_sum_19)
     FDCPE:D                   0.753          serial_sync_count_7
    ----------------------------------------
    Total                      8.117ns (4.567ns logic, 3.550ns route)
                                       (56.3% logic, 43.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK11:O'
Offset:              9.992ns (Levels of Logic = 2)
  Source:            diag_rx_data_7 (FF)
  Destination:       segout<7> (PAD)
  Source Clock:      CLK11:O rising

  Data Path: diag_rx_data_7 to segout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   1.292   1.340  diag_rx_data_7 (diag_rx_data_7)
     LUT2:I1->O            1   0.653   1.150  segout<7>1 (segout_7_OBUF)
     OBUF:I->O                 5.557          segout_7_OBUF (segout<7>)
    ----------------------------------------
    Total                      9.992ns (7.502ns logic, 2.490ns route)
                                       (75.1% logic, 24.9% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               12.884ns (Levels of Logic = 3)
  Source:            reset1 (PAD)
  Destination:       segout<7> (PAD)

  Data Path: reset1 to segout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            48   0.924   4.600  reset1_IBUF (reset1_IBUF)
     LUT2:I0->O            1   0.653   1.150  segout<0>1 (segout_0_OBUF)
     OBUF:I->O                 5.557          segout_0_OBUF (segout<0>)
    ----------------------------------------
    Total                     12.884ns (7.134ns logic, 5.750ns route)
                                       (55.4% logic, 44.6% route)

=========================================================================
CPU : 3.72 / 4.78 s | Elapsed : 4.00 / 5.00 s
 
--> 

Total memory usage is 58948 kilobytes