fpga_lcm.syr

本文件包括多路选择器器建模

                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_11:Q'
Delay:               7.714ns (Levels of Logic = 2)
  Source:            lcm_counter4_0 (FF)
  Destination:       lcm_counter4_2 (FF)
  Source Clock:      lcm_cfgcnt_11:Q falling
  Destination Clock: lcm_cfgcnt_11:Q falling

  Data Path: lcm_counter4_0 to lcm_counter4_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE_1:C->Q           4   1.292   1.600  lcm_counter4_0 (lcm_counter4_0)
     LUT3_D:I1->O          1   0.653   1.150  lcm__n00361 (lcm__n0036)
     LUT4:I0->O            3   0.653   1.480  lcm__n00511 (lcm__n0051)
     FDCE_1:CE                 0.886          lcm_counter4_0
    ----------------------------------------
    Total                      7.714ns (3.484ns logic, 4.230ns route)
                                       (45.2% logic, 54.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_delay_counter_0:Q'
Delay:               4.548ns (Levels of Logic = 1)
  Source:            lcm_delay_counter_1 (FF)
  Destination:       lcm_delay_counter_1 (FF)
  Source Clock:      lcm_delay_counter_0:Q falling
  Destination Clock: lcm_delay_counter_0:Q falling

  Data Path: lcm_delay_counter_1 to lcm_delay_counter_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            6   1.292   1.850  lcm_delay_counter_1 (lcm_delay_counter_1)
     LUT1:I0->O            1   0.653   0.000  lcm__n00451 (lcm__n0045)
     FDC_1:D                   0.753          lcm_delay_counter_1
    ----------------------------------------
    Total                      4.548ns (2.698ns logic, 1.850ns route)
                                       (59.3% logic, 40.7% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_delay_counter_1:Q'
Delay:               4.438ns (Levels of Logic = 1)
  Source:            lcm_delay_counter_2 (FF)
  Destination:       lcm_delay_counter_2 (FF)
  Source Clock:      lcm_delay_counter_1:Q falling
  Destination Clock: lcm_delay_counter_1:Q falling

  Data Path: lcm_delay_counter_2 to lcm_delay_counter_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            5   1.292   1.740  lcm_delay_counter_2 (lcm_delay_counter_2)
     LUT1:I0->O            1   0.653   0.000  lcm__n00481 (lcm__n0048)
     FDC_1:D                   0.753          lcm_delay_counter_2
    ----------------------------------------
    Total                      4.438ns (2.698ns logic, 1.740ns route)
                                       (60.8% logic, 39.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_LCD_state_FFd2:Q'
Delay:               4.898ns (Levels of Logic = 1)
  Source:            lcm_LCD_AC_0 (FF)
  Destination:       lcm_wr_ddram_5 (LATCH)
  Source Clock:      lcm_LCD_state_FFd2:Q falling
  Destination Clock: lcm_LCD_state_FFd2:Q falling

  Data Path: lcm_LCD_AC_0 to lcm_wr_ddram_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           10   1.292   2.200  lcm_LCD_AC_0 (lcm_LCD_AC_0)
     LUT1:I0->O            1   0.653   0.000  lcm__n00521 (lcm__n0052)
     FDC_1:D                   0.753          lcm_LCD_AC_0
    ----------------------------------------
    Total                      4.898ns (2.698ns logic, 2.200ns route)
                                       (55.1% logic, 44.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_LCD_AC_0:Q'
Delay:               4.898ns (Levels of Logic = 1)
  Source:            lcm_LCD_AC_1 (FF)
  Destination:       lcm_LCD_AC_1 (FF)
  Source Clock:      lcm_LCD_AC_0:Q falling
  Destination Clock: lcm_LCD_AC_0:Q falling

  Data Path: lcm_LCD_AC_1 to lcm_LCD_AC_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           10   1.292   2.200  lcm_LCD_AC_1 (lcm_LCD_AC_1)
     LUT1:I0->O            1   0.653   0.000  lcm__n00541 (lcm__n0054)
     FDC_1:D                   0.753          lcm_LCD_AC_1
    ----------------------------------------
    Total                      4.898ns (2.698ns logic, 2.200ns route)
                                       (55.1% logic, 44.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_LCD_AC_1:Q'
Delay:               4.898ns (Levels of Logic = 1)
  Source:            lcm_LCD_AC_2 (FF)
  Destination:       lcm_LCD_AC_2 (FF)
  Source Clock:      lcm_LCD_AC_1:Q falling
  Destination Clock: lcm_LCD_AC_1:Q falling

  Data Path: lcm_LCD_AC_2 to lcm_LCD_AC_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           10   1.292   2.200  lcm_LCD_AC_2 (lcm_LCD_AC_2)
     LUT1:I0->O            1   0.653   0.000  lcm__n00561 (lcm__n0056)
     FDC_1:D                   0.753          lcm_LCD_AC_2
    ----------------------------------------
    Total                      4.898ns (2.698ns logic, 2.200ns route)
                                       (55.1% logic, 44.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_LCD_AC_2:Q'
Delay:               4.818ns (Levels of Logic = 1)
  Source:            lcm_LCD_AC_3 (FF)
  Destination:       lcm_LCD_AC_3 (FF)
  Source Clock:      lcm_LCD_AC_2:Q falling
  Destination Clock: lcm_LCD_AC_2:Q falling

  Data Path: lcm_LCD_AC_3 to lcm_LCD_AC_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            9   1.292   2.120  lcm_LCD_AC_3 (lcm_LCD_AC_3)
     LUT1:I0->O            1   0.653   0.000  lcm__n00581 (lcm__n0058)
     FDC_1:D                   0.753          lcm_LCD_AC_3
    ----------------------------------------
    Total                      4.818ns (2.698ns logic, 2.120ns route)
                                       (56.0% logic, 44.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'lcm_cfgcnt_11:Q'
Offset:              7.999ns (Levels of Logic = 1)
  Source:            lcm_LCD_EN (FF)
  Destination:       E (PAD)
  Source Clock:      lcm_cfgcnt_11:Q falling

  Data Path: lcm_LCD_EN to E
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE_1:C->Q           1   1.292   1.150  lcm_LCD_EN (lcm_LCD_EN)
     OBUF:I->O                 5.557          E_OBUF (E)
    ----------------------------------------
    Total                      7.999ns (6.849ns logic, 1.150ns route)
                                       (85.6% logic, 14.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'lcm__n00331:O'
Offset:              8.128ns (Levels of Logic = 1)
  Source:            lcm_LCD_RS (LATCH)
  Destination:       RS (PAD)
  Source Clock:      lcm__n00331:O falling

  Data Path: lcm_LCD_RS to RS
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.421   1.150  lcm_LCD_RS (lcm_LCD_RS)
     OBUF:I->O                 5.557          RS_OBUF (RS)
    ----------------------------------------
    Total                      8.128ns (6.978ns logic, 1.150ns route)
                                       (85.9% logic, 14.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'lcm__n003210:O'
Offset:              12.534ns (Levels of Logic = 3)
  Source:            lcm_LCD_con_8 (LATCH)
  Destination:       DB0 (PAD)
  Source Clock:      lcm__n003210:O falling

  Data Path: lcm_LCD_con_8 to DB0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               7   1.421   1.950  lcm_LCD_con_8 (lcm_LCD_con_8)
     LUT3:I1->O            1   0.653   1.150  lcm_LCD_DB<1>_SW0 (N1530)
     LUT4:I3->O            1   0.653   1.150  lcm_LCD_DB<1> (DB1_OBUF)
     OBUF:I->O                 5.557          DB1_OBUF (DB1)
    ----------------------------------------
    Total                     12.534ns (8.284ns logic, 4.250ns route)
                                       (66.1% logic, 33.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'lcm_LCD_state_FFd2:Q'
Offset:              11.734ns (Levels of Logic = 3)
  Source:            lcm_wr_ddram_0 (LATCH)
  Destination:       DB0 (PAD)
  Source Clock:      lcm_LCD_state_FFd2:Q falling

  Data Path: lcm_wr_ddram_0 to DB0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.421   1.150  lcm_wr_ddram_0 (lcm_wr_ddram_0)
     LUT3:I2->O            1   0.653   1.150  lcm_LCD_DB<0>_SW0 (N1503)
     LUT4:I3->O            1   0.653   1.150  lcm_LCD_DB<0> (DB0_OBUF)
     OBUF:I->O                 5.557          DB0_OBUF (DB0)
    ----------------------------------------
    Total                     11.734ns (8.284ns logic, 3.450ns route)
                                       (70.6% logic, 29.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'lcm_LCD_AC_0:Q'
Offset:              10.852ns (Levels of Logic = 2)
  Source:            lcm_LCD_AC_1 (FF)
  Destination:       DB1 (PAD)
  Source Clock:      lcm_LCD_AC_0:Q falling

  Data Path: lcm_LCD_AC_1 to DB1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           10   1.292   2.200  lcm_LCD_AC_1 (lcm_LCD_AC_1)
     LUT4:I1->O            1   0.653   1.150  lcm_LCD_DB<1> (DB1_OBUF)
     OBUF:I->O                 5.557          DB1_OBUF (DB1)
    ----------------------------------------
    Total                     10.852ns (7.502ns logic, 3.350ns route)
                                       (69.1% logic, 30.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'lcm_LCD_AC_1:Q'
Offset:              10.852ns (Levels of Logic = 2)
  Source:            lcm_LCD_AC_2 (FF)
  Destination:       DB2 (PAD)
  Source Clock:      lcm_LCD_AC_1:Q falling

  Data Path: lcm_LCD_AC_2 to DB2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           10   1.292   2.200  lcm_LCD_AC_2 (lcm_LCD_AC_2)
     LUT4:I1->O            1   0.653   1.150  lcm_LCD_DB<2> (DB2_OBUF)
     OBUF:I->O                 5.557          DB2_OBUF (DB2)
    ----------------------------------------
    Total                     10.852ns (7.502ns logic, 3.350ns route)
                                       (69.1% logic, 30.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'lcm_LCD_AC_2:Q'
Offset:              10.772ns (Levels of Logic = 2)
  Source:            lcm_LCD_AC_3 (FF)
  Destination:       DB6 (PAD)
  Source Clock:      lcm_LCD_AC_2:Q falling

  Data Path: lcm_LCD_AC_3 to DB6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            9   1.292   2.120  lcm_LCD_AC_3 (lcm_LCD_AC_3)
     LUT4:I1->O            1   0.653   1.150  lcm_LCD_DB<6>1 (DB6_OBUF)
     OBUF:I->O                 5.557          DB6_OBUF (DB6)
    ----------------------------------------
    Total                     10.772ns (7.502ns logic, 3.270ns route)
                                       (69.6% logic, 30.4% route)

=========================================================================
CPU : 4.31 / 6.44 s | Elapsed : 4.00 / 6.00 s
 
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Total memory usage is 57924 kilobytes