fpga_lcm.syr

本文件包括多路选择器器建模

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
lcm__n0033(lcm__n00331:O)          | NONE(*)(lcm_LCD_RS)    | 1     |
lcm_cfgcnt_2:Q                     | NONE                   | 1     |
lcm_cfgcnt_1:Q                     | NONE                   | 1     |
lcm_clock:Q                        | NONE                   | 1     |
lcm_cfgcnt_10:Q                    | NONE                   | 1     |
lcm_cfgcnt_9:Q                     | NONE                   | 1     |
lcm_cfgcnt_8:Q                     | NONE                   | 1     |
lcm_cfgcnt_7:Q                     | NONE                   | 1     |
lcm_cfgcnt_6:Q                     | NONE                   | 1     |
lcm_cfgcnt_5:Q                     | NONE                   | 1     |
lcm_cfgcnt_4:Q                     | NONE                   | 1     |
lcm_cfgcnt_3:Q                     | NONE                   | 1     |
GCLK0                              | BUFGP                  | 1     |
lcm_cfgcnt_11:Q                    | NONE                   | 13    |
lcm_delay_counter_0:Q              | NONE                   | 1     |
lcm_delay_counter_1:Q              | NONE                   | 1     |
lcm_LCD_state_FFd2:Q               | NONE                   | 8     |
lcm_LCD_AC_0:Q                     | NONE                   | 1     |
lcm_LCD_AC_1:Q                     | NONE                   | 1     |
lcm_LCD_AC_2:Q                     | NONE                   | 1     |
lcm__n0032(lcm__n003210:O)         | NONE(*)(lcm_LCD_con_2) | 8     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 7.714ns (Maximum Frequency: 129.634MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 12.534ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_2:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_3 (FF)
  Destination:       lcm_cfgcnt_3 (FF)
  Source Clock:      lcm_cfgcnt_2:Q falling
  Destination Clock: lcm_cfgcnt_2:Q falling

  Data Path: lcm_cfgcnt_3 to lcm_cfgcnt_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_3 (lcm_cfgcnt_3)
     LUT1:I0->O            1   0.653   0.000  lcm__n00651 (lcm__n0065)
     FDC_1:D                   0.753          lcm_cfgcnt_3
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_1:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_2 (FF)
  Destination:       lcm_cfgcnt_2 (FF)
  Source Clock:      lcm_cfgcnt_1:Q falling
  Destination Clock: lcm_cfgcnt_1:Q falling

  Data Path: lcm_cfgcnt_2 to lcm_cfgcnt_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_2 (lcm_cfgcnt_2)
     LUT1:I0->O            1   0.653   0.000  lcm__n00631 (lcm__n0063)
     FDC_1:D                   0.753          lcm_cfgcnt_2
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_clock:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_1 (FF)
  Destination:       lcm_cfgcnt_1 (FF)
  Source Clock:      lcm_clock:Q falling
  Destination Clock: lcm_clock:Q falling

  Data Path: lcm_cfgcnt_1 to lcm_cfgcnt_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_1 (lcm_cfgcnt_1)
     LUT1:I0->O            1   0.653   0.000  lcm__n00611 (lcm__n0061)
     FDC_1:D                   0.753          lcm_cfgcnt_1
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_10:Q'
Delay:               5.298ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_11 (FF)
  Destination:       lcm_cfgcnt_11 (FF)
  Source Clock:      lcm_cfgcnt_10:Q falling
  Destination Clock: lcm_cfgcnt_10:Q falling

  Data Path: lcm_cfgcnt_11 to lcm_cfgcnt_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           14   1.292   2.600  lcm_cfgcnt_11 (lcm_cfgcnt_11)
     LUT1:I0->O            1   0.653   0.000  lcm__n00811 (lcm__n0081)
     FDC_1:D                   0.753          lcm_cfgcnt_11
    ----------------------------------------
    Total                      5.298ns (2.698ns logic, 2.600ns route)
                                       (50.9% logic, 49.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_9:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_10 (FF)
  Destination:       lcm_cfgcnt_10 (FF)
  Source Clock:      lcm_cfgcnt_9:Q falling
  Destination Clock: lcm_cfgcnt_9:Q falling

  Data Path: lcm_cfgcnt_10 to lcm_cfgcnt_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_10 (lcm_cfgcnt_10)
     LUT1:I0->O            1   0.653   0.000  lcm__n00791 (lcm__n0079)
     FDC_1:D                   0.753          lcm_cfgcnt_10
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_8:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_9 (FF)
  Destination:       lcm_cfgcnt_9 (FF)
  Source Clock:      lcm_cfgcnt_8:Q falling
  Destination Clock: lcm_cfgcnt_8:Q falling

  Data Path: lcm_cfgcnt_9 to lcm_cfgcnt_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_9 (lcm_cfgcnt_9)
     LUT1:I0->O            1   0.653   0.000  lcm__n00771 (lcm__n0077)
     FDC_1:D                   0.753          lcm_cfgcnt_9
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_7:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_8 (FF)
  Destination:       lcm_cfgcnt_8 (FF)
  Source Clock:      lcm_cfgcnt_7:Q falling
  Destination Clock: lcm_cfgcnt_7:Q falling

  Data Path: lcm_cfgcnt_8 to lcm_cfgcnt_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_8 (lcm_cfgcnt_8)
     LUT1:I0->O            1   0.653   0.000  lcm__n00751 (lcm__n0075)
     FDC_1:D                   0.753          lcm_cfgcnt_8
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_6:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_7 (FF)
  Destination:       lcm_cfgcnt_7 (FF)
  Source Clock:      lcm_cfgcnt_6:Q falling
  Destination Clock: lcm_cfgcnt_6:Q falling

  Data Path: lcm_cfgcnt_7 to lcm_cfgcnt_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_7 (lcm_cfgcnt_7)
     LUT1:I0->O            1   0.653   0.000  lcm__n00731 (lcm__n0073)
     FDC_1:D                   0.753          lcm_cfgcnt_7
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_5:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_6 (FF)
  Destination:       lcm_cfgcnt_6 (FF)
  Source Clock:      lcm_cfgcnt_5:Q falling
  Destination Clock: lcm_cfgcnt_5:Q falling

  Data Path: lcm_cfgcnt_6 to lcm_cfgcnt_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_6 (lcm_cfgcnt_6)
     LUT1:I0->O            1   0.653   0.000  lcm__n00711 (lcm__n0071)
     FDC_1:D                   0.753          lcm_cfgcnt_6
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_4:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_5 (FF)
  Destination:       lcm_cfgcnt_5 (FF)
  Source Clock:      lcm_cfgcnt_4:Q falling
  Destination Clock: lcm_cfgcnt_4:Q falling

  Data Path: lcm_cfgcnt_5 to lcm_cfgcnt_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_5 (lcm_cfgcnt_5)
     LUT1:I0->O            1   0.653   0.000  lcm__n00691 (lcm__n0069)
     FDC_1:D                   0.753          lcm_cfgcnt_5
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'lcm_cfgcnt_3:Q'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_cfgcnt_4 (FF)
  Destination:       lcm_cfgcnt_4 (FF)
  Source Clock:      lcm_cfgcnt_3:Q falling
  Destination Clock: lcm_cfgcnt_3:Q falling

  Data Path: lcm_cfgcnt_4 to lcm_cfgcnt_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_cfgcnt_4 (lcm_cfgcnt_4)
     LUT1:I0->O            1   0.653   0.000  lcm__n00671 (lcm__n0067)
     FDC_1:D                   0.753          lcm_cfgcnt_4
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)
                                       (66.8% logic, 33.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'GCLK0'
Delay:               4.038ns (Levels of Logic = 1)
  Source:            lcm_clock (FF)
  Destination:       lcm_clock (FF)
  Source Clock:      GCLK0 falling
  Destination Clock: GCLK0 falling

  Data Path: lcm_clock to lcm_clock
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcm_clock (lcm_clock)
     LUT1:I0->O            1   0.653   0.000  lcm__n00601 (lcm__n0060)
     FDC_1:D                   0.753          lcm_clock
    ----------------------------------------
    Total                      4.038ns (2.698ns logic, 1.340ns route)