fpga_lcm.syr

本文件包括多路选择器器建模

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.30 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.31 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: fpga_lcm.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : fpga_lcm.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : fpga_lcm
Output Format                      : NGC
Target Device                      : xc2s200-5-pq208

---- Source Options
Top Module Name                    : fpga_lcm
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : fpga_lcm.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "rom_32x8.v"
Module <rom_32x8> compiled
Compiling source file "lcm.v"
Module <lcm> compiled
Compiling source file "fpga_lcm.v"
Module <fpga_lcm> compiled
No errors in compilation
Analysis of file <fpga_lcm.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <fpga_lcm>.
Module <fpga_lcm> is correct for synthesis.
 
Analyzing module <lcm>.
WARNING:Xst:905 - lcm.v line 128: The signals <q1> are missing in the sensitivity list of always block.
Module <lcm> is correct for synthesis.
 
Analyzing module <rom_32x8>.
Module <rom_32x8> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <LCD_RW> in unit <lcm> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <rom_32x8>.
    Related source file is rom_32x8.v.
    Found 16x8-bit ROM for signal <dout>.
    Summary:
	inferred   1 ROM(s).
Unit <rom_32x8> synthesized.


Synthesizing Unit <lcm>.
    Related source file is lcm.v.
    Found finite state machine <FSM_0> for signal <LCD_state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 8                                              |
    | Inputs             | 0                                              |
    | Outputs            | 8                                              |
    | Clock              | syn_clock (falling_edge)                       |
    | Clock enable       | $n0000 (positive)                              |
    | Reset              | restart (positive)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00000001                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 8-bit latch for signal <wr_ddram>.
    Using one-hot encoding for signal <LCD_con>.
WARNING:Xst:737 - Found 9-bit latch for signal <LCD_con>.
WARNING:Xst:737 - Found 1-bit latch for signal <LCD_RS>.
    Found 1-bit register for signal <LCD_EN>.
    Found 11-bit register for signal <cfgcnt>.
    Found 1-bit register for signal <clock>.
    Found 3-bit up counter for signal <counter4>.
    Found 3-bit register for signal <delay_counter>.
    Found 4-bit register for signal <LCD_AC>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  20 D-type flip-flop(s).
Unit <lcm> synthesized.


Synthesizing Unit <fpga_lcm>.
    Related source file is fpga_lcm.v.
Unit <fpga_lcm> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <LCD_state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Counters                         : 1
 3-bit up counter                  : 1
# Registers                        : 28
 1-bit register                    : 28
# Latches                          : 3
 1-bit latch                       : 1
 9-bit latch                       : 1
 8-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <LCD_con_6> (without init value) is constant in block <lcm>.
WARNING:Xst:1710 - FF/Latch  <LCD_con_5> (without init value) is constant in block <lcm>.
WARNING:Xst:1710 - FF/Latch  <wr_ddram_7> (without init value) is constant in block <lcm>.

Optimizing unit <fpga_lcm> ...

Optimizing unit <lcm> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fpga_lcm, actual ratio is 1.
Latch lcm_LCD_con_7 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fpga_lcm.ngr
Top Level Output File Name         : fpga_lcm
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 21
#      1-bit register              : 20
#      3-bit register              : 1

Cell Usage :
# BELS                             : 52
#      GND                         : 1
#      LUT1                        : 20
#      LUT2                        : 5
#      LUT3                        : 9
#      LUT3_D                      : 1
#      LUT4                        : 16
# FlipFlops/Latches                : 47
#      FDC_1                       : 19
#      FDCE_1                      : 11
#      FDPE_1                      : 1
#      LD                          : 16
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 1
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-5 

 Number of Slices:                      29  out of   2352     1%  
 Number of Slice Flip Flops:            47  out of   4704     0%  
 Number of 4 input LUTs:                51  out of   4704     1%  
 Number of bonded IOBs:                 12  out of    144     8%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.