lcm.v

本文件包括多路选择器器建模

//write by ppkliu 2003.05.11

//module lcm(clkorg,r1,r2,LCD_RS,LCD_RW,LCD_EN,LCD_DB);
module lcm(clkorg,restart,LCD_RS,LCD_RW,LCD_EN,LCD_DB);

output [7:0] LCD_DB;
output LCD_RW,LCD_RS,LCD_EN;
input restart;
input clkorg;


reg LCD_RW;
reg LCD_RS; 
reg LCD_EN;

reg[11:1] cfgcnt;		  
wire cfgcnt_1=cfgcnt[1];
wire cfgcnt_2=cfgcnt[2];
wire cfgcnt_3=cfgcnt[3];
wire cfgcnt_4=cfgcnt[4];
wire cfgcnt_5=cfgcnt[5];
wire cfgcnt_6=cfgcnt[6];
wire cfgcnt_7=cfgcnt[7];
wire cfgcnt_8=cfgcnt[8];
wire cfgcnt_9=cfgcnt[9];
wire cfgcnt_10=cfgcnt[10];
wire cfgcnt_11=cfgcnt[11];
//control pins
reg [2:0]delay_counter;

parameter
   fun_set=4'b0000,LCD_off=4'b0001,
   clr_lcd=4'b0010,in_mode=4'b0011,
   LCD_on=4'b0100,cur_con=4'b0101,
   cur_home=4'b0110,dd_addr=4'b0111,
   wr_data=4'b1000,config_rom=4'b1001,
   nop=4'b1010,fun_set1=4'b1011,
   fun_set2=4'b1100,fun_set3=4'b1101;
parameter
   LCD_hlt=8'b00000000;

reg [3:0]LCD_AC;//4:0
reg [2:0]counter4;
reg [3:0]LCD_state;
reg [3:0]LCD_con;
reg [3:0]LCD_next;
reg [7:0]wr_ddram;
wire [7:0]dd_address;

assign dd_address[7:3]=({1'b1,LCD_AC[3],3'b000});
assign dd_address[2:0]=LCD_AC[2:0];					

wire [7:0]q1;//data out from memory

rom_32x8 LCD_RAM1 (.dout(q1[7:0]),.addre(LCD_AC[3:0])); 

assign LCD_DB=(1'b1)?(
   (LCD_con==clr_lcd) ? 8'b0000_0001:
   (LCD_con==cur_home)? 8'b0000_0010:
   (LCD_con==in_mode) ? 8'b0000_0110:
   (LCD_con==LCD_on)  ? 8'b0000_1111:
   (LCD_con==LCD_off) ? 8'b0000_1000:
   (LCD_con==cur_con) ? 8'b0001_0100:
   (LCD_con==fun_set) ? 8'b0011_1000: 
   (LCD_con==dd_addr) ? dd_address :
   (LCD_con==wr_data) ? wr_ddram :
   (LCD_con==nop) ?  LCD_hlt:
    LCD_hlt):
   (LCD_hlt);
//T = 10.95ms

//周期分割
wire syn_clock=cfgcnt_11;

always @(posedge restart or negedge syn_clock)
	if(restart)
	 delay_counter[0]<=0;
	else 
	 delay_counter[0]<=!delay_counter[0];
always @(posedge restart or negedge delay_counter[0])
	if(restart)
	 delay_counter[1]<=0; 
	else
	 delay_counter[1]<=!delay_counter[1];
always @(posedge restart or negedge delay_counter[1])
	 if(restart)
         delay_counter[2]<=0;    
	 else
	  delay_counter[2]<=!delay_counter[2];	
	
wire en_hi=(delay_counter[2:0]==3'b011); //3*T
wire en_lo=(delay_counter[2:0]==3'b101); //5*T

always @(posedge restart or negedge syn_clock)
begin
  if(restart) LCD_EN=1'b0;
  else if (en_hi)LCD_EN=1'b1;
  else if (en_lo)LCD_EN=1'b0;
end


//swicth the FSM   
always @(posedge restart or negedge syn_clock)
begin
   if(restart)
    begin
     counter4=3'b000; 
     LCD_state=fun_set;
    end   
     else if(delay_counter==3'b111)
      begin
       if(counter4==3'b100)
        begin
 	      LCD_state=LCD_next; 
         end       
        else
         begin
          counter4=counter4+1'b1;
        end
      end    

end

//LCD State FSM

always@(LCD_state)
begin 
    LCD_next=LCD_state;  
     case(LCD_state)
       fun_set:
         begin
           LCD_RW=1'b0;
		   LCD_RS=1'b0;
           LCD_next=LCD_off;        
           LCD_con=fun_set;
         end
       
       LCD_off:
         begin  
          LCD_next=clr_lcd;
          LCD_con=LCD_off;
         end
       clr_lcd:
         begin         
          LCD_next=in_mode;
          LCD_con=clr_lcd;
         end 
       in_mode:
         begin
          LCD_next=LCD_on;
          LCD_con=in_mode;
         end
       LCD_on:
         begin
          LCD_next=dd_addr;
          LCD_con=LCD_on;
         end
       dd_addr:
         begin//dd_address
		   LCD_next=config_rom;     
	       LCD_con=dd_addr;
         end  
       wr_data:
	     begin
		  LCD_RS=1'b1;		
          LCD_RW=1'b0;
		  LCD_next=config_rom;
          LCD_con=wr_data; 
         end
        config_rom: //setup address
		 begin
		  LCD_RS=1'b0;
		  LCD_RW=1'b0;
		  wr_ddram=q1;
		  LCD_next=wr_data;     	
          LCD_con=dd_addr;	
         end 
       default:
         begin
          LCD_next=fun_set;
		 end
         endcase
  
end

wire AC_1=(LCD_state[3:0]==config_rom);
wire AC_W0=LCD_AC[0];
wire AC_W1=LCD_AC[1];
wire AC_W2=LCD_AC[2];

always@(posedge restart or negedge AC_1)
  if(restart)LCD_AC[0]=1'b0;
  else LCD_AC[0]=!LCD_AC[0];
always@(posedge restart or negedge AC_W0)
  if(restart)LCD_AC[1]=1'b0;
  else LCD_AC[1]=!LCD_AC[1];
always@(posedge restart or negedge AC_W1)
  if(restart)LCD_AC[2]=1'b0;
  else LCD_AC[2]=!LCD_AC[2];
always@(posedge restart or negedge AC_W2)
  if(restart)LCD_AC[3]=1'b0;
  else LCD_AC[3]=!LCD_AC[3];


reg clock;
always@( posedge restart or negedge clkorg) //12Mhz
 begin
  if (restart)clock=0;
  else clock=!clock;      //6MHZ
 end 
//16bits counters,counter the freqency


always @(posedge restart or negedge clock)//3M 
	if(restart)cfgcnt[1]<=0;
	else cfgcnt[1]<=!cfgcnt[1];
always @(posedge restart or negedge cfgcnt_1)//1.5M 
	if(restart)cfgcnt[2]<=0;
	else cfgcnt[2]<=!cfgcnt[2];
always @(posedge restart or negedge cfgcnt_2)//0.75K 0.75
	if(restart)cfgcnt[3]<=0;
	else cfgcnt[3]<=!cfgcnt[3];
always @(posedge restart or negedge cfgcnt_3)//375K
	if(restart)cfgcnt[4]<=0;
	else cfgcnt[4]<=!cfgcnt[4];
always @(posedge restart or negedge cfgcnt_4)//187.5K
	if(restart)cfgcnt[5]<=0;
	else cfgcnt[5]<=!cfgcnt[5];
always @(posedge restart or negedge cfgcnt_5)//93.75K
	if(restart)cfgcnt[6]<=0;
	else cfgcnt[6]<=!cfgcnt[6];
always @(posedge restart or negedge cfgcnt_6)//46.875K
	if(restart)cfgcnt[7]<=0;
	else cfgcnt[7]<=!cfgcnt[7];

always @(posedge restart or negedge cfgcnt_7)//23.43K
	if(restart)cfgcnt[8]<=0;
	else cfgcnt[8]<=!cfgcnt[8];
always @(posedge restart or negedge cfgcnt_8)//11.71K
	if(restart)cfgcnt[9]<=0;
	else cfgcnt[9]<=!cfgcnt[9];
always @(posedge restart or negedge cfgcnt_9)//5.85K
	if(restart)cfgcnt[10]<=0;
	else cfgcnt[10]<=!cfgcnt[10];

always @(posedge restart or negedge cfgcnt_10)//2K
	if(restart)cfgcnt[11]<=0;
	else cfgcnt[11]<=!cfgcnt[11];	

endmodule