halfadder.vhd

来自「application of a galois field multiplica」· VHDL 代码 · 共 22 行

Library ieee ;
use ieee.std_logic_1164.all;

entity hadder is
   port (
            a  : in  std_logic;
            b  : in  std_logic;
            s  : out std_logic;
            co : out std_logic
         );
end hadder;

architecture hadder_rtl of hadder is
begin

        s     <=  a xor b ;
        co    <=  a and b ;
     
end hadder_rtl;