fadder.vhd

来自「application of a galois field multiplica」· VHDL 代码 · 共 21 行

Library ieee ;
use ieee.std_logic_1164.all;

entity fadder is --full-adder
   port (
            a  : in  std_logic;
            b  : in  std_logic;
            ci : in  std_logic;
            s  : out std_logic;
            co : out std_logic
         );
end fadder;

architecture fadder_rtl of fadder is

begin

        s     <=  a xor b xor ci ;
        co    <=  (a AND b) OR ( ci AND (a OR b)) ;
end fadder_rtl;