reg16.vhd

来自「application of a galois field multiplica」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity reg16 is   -- a 16-bit register
	 port(
		 CLK : in std_logic;
		 Rst : in std_logic;
		 enable : in std_logic;
		 Data_in : in std_logic_vector(15 downto 0);	
		 Data_out : out std_logic_vector(15 downto 0)
	     );
end reg16;

architecture arch_reg16 of reg16 is			 

	signal temp :  std_logic_vector(15 downto 0);
begin

	process( CLK, Rst)
	begin					   
		if Rst = '1' then
			temp <= (others => '0');
		elsif
			enable = '1' and CLK'event and CLK = '1' then
			temp <= data_in;  
		end if;
	end process;
	data_out <= temp;	

end arch_reg16;