top_mult.vhd.bak

application of a galois field multiplication and normal multiplication

Library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- for power analysis only
entity top_mult is		   -- the FF multiplier with registers at input and output stages
  	port (
	    CLK : in std_logic;
	    Rst : in std_logic;
	    enable : in std_logic;
	    cont : in std_logic;            
        a    : in  std_logic_vector(7 downto 0);
        b    : in  std_logic_vector(7 downto 0);
        p    : in  std_logic_vector(7 downto 0);
        s    : out std_logic_vector(15 downto 0));
           
end top_mult;

architecture top_mult_rtl of top_mult is

	component gff3 is	  -- the FF multiplier
   	port (
           
            a    : in  std_logic_vector(7 downto 0);
            b    : in  std_logic_vector(7 downto 0);
            p    : in  std_logic_vector(7 downto 0);
            s    : out std_logic_vector(15 downto 0)
         );
	end component;
	    	
	component reg8 is -- 8-bit register
	port(	 CLK : in std_logic;
		 Rst : in std_logic;
		 enable : in std_logic;
		 Data_in : in std_logic_vector(7 downto 0);	 	
		 Data_out : out std_logic_vector(7 downto 0));
	end component;
	
	component reg16 is 	  -- 16-bit register
	port(	 CLK : in std_logic;
		 Rst : in std_logic;
		 enable : in std_logic;
		 Data_in : in std_logic_vector(15 downto 0);	 	
		 Data_out : out std_logic_vector(15 downto 0));
	end component;        
	        
        signal aa,bb,pp: std_logic_vector(7 downto 0);
   	signal mul_out,ss  : std_logic_vector(15 downto 0);

begin      
      reg0 : reg8 port map(CLK => CLK, Rst => Rst, enable => enable, Data_in => a, Data_out => aa);
      reg1 : reg8 port map(CLK => CLK, Rst => Rst, enable => enable, Data_in => b, Data_out => bb);
      reg2 : reg8 port map(CLK => CLK, Rst => Rst, enable => enable, Data_in => p, Data_out => pp);	
      gff0 : gff3 port map(cont,aa,bb,pp,mul_out);
      reg3 : reg16 port map(CLK => CLK, Rst => Rst, enable => enable, Data_in => mul_out, Data_out => ss);      
      s <= ss;
	 
end top_mult_rtl;