mod8_1.vhd

来自「application of a galois field multiplica」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;

entity mod8_1 is
port(
a: in std_logic;
b: in std_logic_vector( 7 downto 0);
c: in std_logic_vector( 7 downto 0);
s: out std_logic_vector(7 downto 0));
end entity mod8_1;

architecture mod8_1_rtl of mod8_1 is
begin
s(7) <= ( a and b(7)) xor c(7);
s(6) <= ( a and b(6)) xor c(6);
s(5) <= ( a and b(5)) xor c(5);
s(4) <= ( a and b(4)) xor c(4);
s(3) <= ( a and b(3)) xor c(3);
s(2) <= ( a and b(2)) xor c(2);
s(1) <= ( a and b(1)) xor c(1);
s(0) <= ( a and b(0)) xor c(0);
end architecture mod8_1_rtl;