mod_teil.vhd

application of a galois field multiplication and normal multiplication

library ieee;
use ieee.std_logic_1164.all;

entity mod_teil is
    port(
    a: in std_logic_vector( 15 downto 0);
    p: in std_logic_vector( 7 downto 0);
    s: out std_logic_vector( 15 downto 0));
end entity mod_teil;

architecture mod_teil_rtl of mod_teil is
    
signal ss1,ss2,ss3,ss4,ss5,ss6: std_logic_vector ( 7 downto 0);
signal s1, s2, s3, s4, s5, s6, s7: std_logic_vector (7 downto 0);

component mod8_1 is
port(
a: in std_logic;
b: in std_logic_vector( 7 downto 0);
c: in std_logic_vector( 7 downto 0);
s: out std_logic_vector(7 downto 0));
end component;
    
begin
--modulorechnen

mod8_1_1 : mod8_1 port map (a(14),p,a(13 downto 6),s1);

ss1 <= s1(6 downto 0) & a(5);
mod8_1_2 : mod8_1 port map (s1(7),p,ss1, s2);

ss2 <= s2(6 downto 0) & a(4);
mod8_1_3 : mod8_1 port map (s2(7),p,ss2,s3);

ss3 <= s3(6 downto 0) & a(3);
mod8_1_4 : mod8_1 port map (s3(7),p,ss3,s4);

ss4 <= s4(6 downto 0) & a(2);
mod8_1_5 : mod8_1 port map (s4(7),p,ss4,s5);

ss5 <= s5(6 downto 0) & a(1);
mod8_1_6 : mod8_1 port map (s5(7),p,ss5,s6);

ss6 <= s6(6 downto 0) & a(0);
mod8_1_7 : mod8_1 port map (s6(7),p,ss6,s7);

s <= "00000000" & s7;

end architecture mod_teil_rtl;