mypinlvji.tan.qmsg

该程序实现一个频率计

{ "Info" "ITDB_FULL_TCO_RESULT" "clk 78leddata\[2\] pinlvji:inst1\|cntq5\[2\] 18.560 ns register " "Info: tco from clock \"clk\" to destination pin \"78leddata\[2\]\" through register \"pinlvji:inst1\|cntq5\[2\]\" is 18.560 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.649 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypinlvji.bdf" "" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { { 64 -80 88 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.970 ns) 3.670 ns int_div:inst2\|clk_tem 2 REG LCFF_X21_Y7_N21 2 " "Info: 2: + IC(1.560 ns) + CELL(0.970 ns) = 3.670 ns; Loc. = LCFF_X21_Y7_N21; Fanout = 2; REG Node = 'int_div:inst2\|clk_tem'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.530 ns" { clk int_div:inst2|clk_tem } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.475 ns) + CELL(0.000 ns) 5.145 ns int_div:inst2\|clk_tem~clkctrl 3 COMB CLKCTRL_G5 64 " "Info: 3: + IC(1.475 ns) + CELL(0.000 ns) = 5.145 ns; Loc. = CLKCTRL_G5; Fanout = 64; COMB Node = 'int_div:inst2\|clk_tem~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.475 ns" { int_div:inst2|clk_tem int_div:inst2|clk_tem~clkctrl } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 6.649 ns pinlvji:inst1\|cntq5\[2\] 4 REG LCFF_X17_Y8_N7 1 " "Info: 4: + IC(0.838 ns) + CELL(0.666 ns) = 6.649 ns; Loc. = LCFF_X17_Y8_N7; Fanout = 1; REG Node = 'pinlvji:inst1\|cntq5\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { int_div:inst2|clk_tem~clkctrl pinlvji:inst1|cntq5[2] } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 41.75 % ) " "Info: Total cell delay = 2.776 ns ( 41.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.873 ns ( 58.25 % ) " "Info: Total interconnect delay = 3.873 ns ( 58.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.649 ns" { clk int_div:inst2|clk_tem int_div:inst2|clk_tem~clkctrl pinlvji:inst1|cntq5[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.649 ns" { clk {} clk~combout {} int_div:inst2|clk_tem {} int_div:inst2|clk_tem~clkctrl {} pinlvji:inst1|cntq5[2] {} } { 0.000ns 0.000ns 1.560ns 1.475ns 0.838ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.607 ns + Longest register pin " "Info: + Longest register to pin delay is 11.607 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pinlvji:inst1\|cntq5\[2\] 1 REG LCFF_X17_Y8_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y8_N7; Fanout = 1; REG Node = 'pinlvji:inst1\|cntq5\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { pinlvji:inst1|cntq5[2] } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.206 ns) 1.296 ns pinlvji:inst1\|Mux9~39 2 COMB LCCOMB_X15_Y8_N12 1 " "Info: 2: + IC(1.090 ns) + CELL(0.206 ns) = 1.296 ns; Loc. = LCCOMB_X15_Y8_N12; Fanout = 1; COMB Node = 'pinlvji:inst1\|Mux9~39'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.296 ns" { pinlvji:inst1|cntq5[2] pinlvji:inst1|Mux9~39 } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.624 ns) 2.938 ns pinlvji:inst1\|Mux9~40 3 COMB LCCOMB_X15_Y8_N24 1 " "Info: 3: + IC(1.018 ns) + CELL(0.624 ns) = 2.938 ns; Loc. = LCCOMB_X15_Y8_N24; Fanout = 1; COMB Node = 'pinlvji:inst1\|Mux9~40'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { pinlvji:inst1|Mux9~39 pinlvji:inst1|Mux9~40 } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.389 ns) + CELL(0.651 ns) 4.978 ns pinlvji:inst1\|Mux9~41 4 COMB LCCOMB_X18_Y7_N24 7 " "Info: 4: + IC(1.389 ns) + CELL(0.651 ns) = 4.978 ns; Loc. = LCCOMB_X18_Y7_N24; Fanout = 7; COMB Node = 'pinlvji:inst1\|Mux9~41'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.040 ns" { pinlvji:inst1|Mux9~40 pinlvji:inst1|Mux9~41 } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.825 ns) + CELL(0.624 ns) 7.427 ns pinlvji:inst1\|Mux16~19 5 COMB LCCOMB_X27_Y7_N10 1 " "Info: 5: + IC(1.825 ns) + CELL(0.624 ns) = 7.427 ns; Loc. = LCCOMB_X27_Y7_N10; Fanout = 1; COMB Node = 'pinlvji:inst1\|Mux16~19'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.449 ns" { pinlvji:inst1|Mux9~41 pinlvji:inst1|Mux16~19 } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.074 ns) + CELL(3.106 ns) 11.607 ns 78leddata\[2\] 6 PIN PIN_116 0 " "Info: 6: + IC(1.074 ns) + CELL(3.106 ns) = 11.607 ns; Loc. = PIN_116; Fanout = 0; PIN Node = '78leddata\[2\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.180 ns" { pinlvji:inst1|Mux16~19 78leddata[2] } "NODE_NAME" } } { "mypinlvji.bdf" "" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { { 120 488 664 136 "78leddata\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.211 ns ( 44.90 % ) " "Info: Total cell delay = 5.211 ns ( 44.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.396 ns ( 55.10 % ) " "Info: Total interconnect delay = 6.396 ns ( 55.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.607 ns" { pinlvji:inst1|cntq5[2] pinlvji:inst1|Mux9~39 pinlvji:inst1|Mux9~40 pinlvji:inst1|Mux9~41 pinlvji:inst1|Mux16~19 78leddata[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "11.607 ns" { pinlvji:inst1|cntq5[2] {} pinlvji:inst1|Mux9~39 {} pinlvji:inst1|Mux9~40 {} pinlvji:inst1|Mux9~41 {} pinlvji:inst1|Mux16~19 {} 78leddata[2] {} } { 0.000ns 1.090ns 1.018ns 1.389ns 1.825ns 1.074ns } { 0.000ns 0.206ns 0.624ns 0.651ns 0.624ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.649 ns" { clk int_div:inst2|clk_tem int_div:inst2|clk_tem~clkctrl pinlvji:inst1|cntq5[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.649 ns" { clk {} clk~combout {} int_div:inst2|clk_tem {} int_div:inst2|clk_tem~clkctrl {} pinlvji:inst1|cntq5[2] {} } { 0.000ns 0.000ns 1.560ns 1.475ns 0.838ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "11.607 ns" { pinlvji:inst1|cntq5[2] pinlvji:inst1|Mux9~39 pinlvji:inst1|Mux9~40 pinlvji:inst1|Mux9~41 pinlvji:inst1|Mux16~19 78leddata[2] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "11.607 ns" { pinlvji:inst1|cntq5[2] {} pinlvji:inst1|Mux9~39 {} pinlvji:inst1|Mux9~40 {} pinlvji:inst1|Mux9~41 {} pinlvji:inst1|Mux16~19 {} 78leddata[2] {} } { 0.000ns 1.090ns 1.018ns 1.389ns 1.825ns 1.074ns } { 0.000ns 0.206ns 0.624ns 0.651ns 0.624ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 28 14:55:35 2008 " "Info: Processing ended: Wed May 28 14:55:35 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}