mypinlvji.fnsim.qmsg

该程序实现一个频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 28 14:19:42 2008 " "Info: Processing started: Wed May 28 14:19:42 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mypinlvji -c mypinlvji --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mypinlvji -c mypinlvji --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mypinlvji.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file mypinlvji.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 mypinlvji " "Info: Found entity 1: mypinlvji" {  } { { "mypinlvji.bdf" "" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pinlvji.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pinlvji.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pinlvji-one " "Info: Found design unit 1: pinlvji-one" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pinlvji " "Info: Found entity 1: pinlvji" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file int_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int_div-behav " "Info: Found design unit 1: int_div-behav" {  } { { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 int_div " "Info: Found entity 1: int_div" {  } { { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pinlvji " "Info: Elaborating entity \"pinlvji\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "seg7 pinlvji.vhd(80) " "Warning (10631): VHDL Process Statement warning at pinlvji.vhd(80): inferring latch(es) for signal or variable \"seg7\", which holds its previous value in one or more paths through the process" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 80 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg7\[0\] pinlvji.vhd(80) " "Info (10041): Inferred latch for \"seg7\[0\]\" at pinlvji.vhd(80)" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg7\[1\] pinlvji.vhd(80) " "Info (10041): Inferred latch for \"seg7\[1\]\" at pinlvji.vhd(80)" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg7\[2\] pinlvji.vhd(80) " "Info (10041): Inferred latch for \"seg7\[2\]\" at pinlvji.vhd(80)" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg7\[3\] pinlvji.vhd(80) " "Info (10041): Inferred latch for \"seg7\[3\]\" at pinlvji.vhd(80)" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg7\[4\] pinlvji.vhd(80) " "Info (10041): Inferred latch for \"seg7\[4\]\" at pinlvji.vhd(80)" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg7\[5\] pinlvji.vhd(80) " "Info (10041): Inferred latch for \"seg7\[5\]\" at pinlvji.vhd(80)" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg7\[6\] pinlvji.vhd(80) " "Info (10041): Inferred latch for \"seg7\[6\]\" at pinlvji.vhd(80)" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 80 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "20 " "Info: Inferred 20 megafunctions from design logic" { { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux0\"" {  } { { "pinlvji.vhd" "Mux0" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux1\"" {  } { { "pinlvji.vhd" "Mux1" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux2\"" {  } { { "pinlvji.vhd" "Mux2" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux3\"" {  } { { "pinlvji.vhd" "Mux3" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux4\"" {  } { { "pinlvji.vhd" "Mux4" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux5\"" {  } { { "pinlvji.vhd" "Mux5" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux6\"" {  } { { "pinlvji.vhd" "Mux6" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux7 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux7\"" {  } { { "pinlvji.vhd" "Mux7" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux8 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux8\"" {  } { { "pinlvji.vhd" "Mux8" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux9 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux9\"" {  } { { "pinlvji.vhd" "Mux9" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux10 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux10\"" {  } { { "pinlvji.vhd" "Mux10" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux11 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux11\"" {  } { { "pinlvji.vhd" "Mux11" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux12 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux12\"" {  } { { "pinlvji.vhd" "Mux12" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux13 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux13\"" {  } { { "pinlvji.vhd" "Mux13" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux14 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux14\"" {  } { { "pinlvji.vhd" "Mux14" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux15 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux15\"" {  } { { "pinlvji.vhd" "Mux15" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 67 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux16 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux16\"" {  } { { "pinlvji.vhd" "Mux16" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux17 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux17\"" {  } { { "pinlvji.vhd" "Mux17" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux18 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux18\"" {  } { { "pinlvji.vhd" "Mux18" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux19 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux19\"" {  } { { "pinlvji.vhd" "Mux19" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "e:/altera/quartus/libraries/megafunctions/lpm_mux.tdf" 74 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux0\"" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 82 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_joc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_joc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_joc " "Info: Found entity 1: mux_joc" {  } { { "db/mux_joc.tdf" "" { Text "E:/Altera/myvhdl/mypinlvji/db/mux_joc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}