prev_cmp_mypinlvji.tan.qmsg

该程序实现一个频率计

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "int_div:inst\|clk_tem " "Info: Detected ripple clock \"int_div:inst\|clk_tem\" as buffer" {  } { { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 20 -1 0 } } { "e:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "int_div:inst\|clk_tem" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register pinlvji:inst1\|cntp5\[0\] register pinlvji:inst1\|cntp5\[3\] 150.4 MHz 6.649 ns Internal " "Info: Clock \"clk\" has Internal fmax of 150.4 MHz between source register \"pinlvji:inst1\|cntp5\[0\]\" and destination register \"pinlvji:inst1\|cntp5\[3\]\" (period= 6.649 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.385 ns + Longest register register " "Info: + Longest register to register delay is 6.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pinlvji:inst1\|cntp5\[0\] 1 REG LCFF_X15_Y6_N27 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y6_N27; Fanout = 6; REG Node = 'pinlvji:inst1\|cntp5\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { pinlvji:inst1|cntp5[0] } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.950 ns) + CELL(0.534 ns) 2.484 ns pinlvji:inst1\|process1~256 2 COMB LCCOMB_X15_Y7_N4 1 " "Info: 2: + IC(1.950 ns) + CELL(0.534 ns) = 2.484 ns; Loc. = LCCOMB_X15_Y7_N4; Fanout = 1; COMB Node = 'pinlvji:inst1\|process1~256'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { pinlvji:inst1|cntp5[0] pinlvji:inst1|process1~256 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.380 ns) + CELL(0.370 ns) 3.234 ns pinlvji:inst1\|process1~258 3 COMB LCCOMB_X15_Y7_N14 2 " "Info: 3: + IC(0.380 ns) + CELL(0.370 ns) = 3.234 ns; Loc. = LCCOMB_X15_Y7_N14; Fanout = 2; COMB Node = 'pinlvji:inst1\|process1~258'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.750 ns" { pinlvji:inst1|process1~256 pinlvji:inst1|process1~258 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.379 ns) + CELL(0.616 ns) 4.229 ns pinlvji:inst1\|cntq1\[3\]~36 4 COMB LCCOMB_X15_Y7_N0 44 " "Info: 4: + IC(0.379 ns) + CELL(0.616 ns) = 4.229 ns; Loc. = LCCOMB_X15_Y7_N0; Fanout = 44; COMB Node = 'pinlvji:inst1\|cntq1\[3\]~36'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.995 ns" { pinlvji:inst1|process1~258 pinlvji:inst1|cntq1[3]~36 } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(0.370 ns) 5.713 ns pinlvji:inst1\|cntp6~468 5 COMB LCCOMB_X15_Y6_N2 1 " "Info: 5: + IC(1.114 ns) + CELL(0.370 ns) = 5.713 ns; Loc. = LCCOMB_X15_Y6_N2; Fanout = 1; COMB Node = 'pinlvji:inst1\|cntp6~468'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.484 ns" { pinlvji:inst1|cntq1[3]~36 pinlvji:inst1|cntp6~468 } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.358 ns) + CELL(0.206 ns) 6.277 ns pinlvji:inst1\|cntp5~580 6 COMB LCCOMB_X15_Y6_N16 1 " "Info: 6: + IC(0.358 ns) + CELL(0.206 ns) = 6.277 ns; Loc. = LCCOMB_X15_Y6_N16; Fanout = 1; COMB Node = 'pinlvji:inst1\|cntp5~580'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.564 ns" { pinlvji:inst1|cntp6~468 pinlvji:inst1|cntp5~580 } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.385 ns pinlvji:inst1\|cntp5\[3\] 7 REG LCFF_X15_Y6_N17 4 " "Info: 7: + IC(0.000 ns) + CELL(0.108 ns) = 6.385 ns; Loc. = LCFF_X15_Y6_N17; Fanout = 4; REG Node = 'pinlvji:inst1\|cntp5\[3\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { pinlvji:inst1|cntp5~580 pinlvji:inst1|cntp5[3] } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.204 ns ( 34.52 % ) " "Info: Total cell delay = 2.204 ns ( 34.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.181 ns ( 65.48 % ) " "Info: Total interconnect delay = 4.181 ns ( 65.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.385 ns" { pinlvji:inst1|cntp5[0] pinlvji:inst1|process1~256 pinlvji:inst1|process1~258 pinlvji:inst1|cntq1[3]~36 pinlvji:inst1|cntp6~468 pinlvji:inst1|cntp5~580 pinlvji:inst1|cntp5[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.385 ns" { pinlvji:inst1|cntp5[0] {} pinlvji:inst1|process1~256 {} pinlvji:inst1|process1~258 {} pinlvji:inst1|cntq1[3]~36 {} pinlvji:inst1|cntp6~468 {} pinlvji:inst1|cntp5~580 {} pinlvji:inst1|cntp5[3] {} } { 0.000ns 1.950ns 0.380ns 0.379ns 1.114ns 0.358ns 0.000ns } { 0.000ns 0.534ns 0.370ns 0.616ns 0.370ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.624 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.624 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypinlvji.bdf" "" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { { 64 -80 88 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.559 ns) + CELL(0.970 ns) 3.669 ns int_div:inst\|clk_tem 2 REG LCFF_X21_Y7_N13 2 " "Info: 2: + IC(1.559 ns) + CELL(0.970 ns) = 3.669 ns; Loc. = LCFF_X21_Y7_N13; Fanout = 2; REG Node = 'int_div:inst\|clk_tem'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.529 ns" { clk int_div:inst|clk_tem } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.473 ns) + CELL(0.000 ns) 5.142 ns int_div:inst\|clk_tem~clkctrl 3 COMB CLKCTRL_G5 64 " "Info: 3: + IC(1.473 ns) + CELL(0.000 ns) = 5.142 ns; Loc. = CLKCTRL_G5; Fanout = 64; COMB Node = 'int_div:inst\|clk_tem~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.666 ns) 6.624 ns pinlvji:inst1\|cntp5\[3\] 4 REG LCFF_X15_Y6_N17 4 " "Info: 4: + IC(0.816 ns) + CELL(0.666 ns) = 6.624 ns; Loc. = LCFF_X15_Y6_N17; Fanout = 4; REG Node = 'pinlvji:inst1\|cntp5\[3\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.482 ns" { int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp5[3] } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 41.91 % ) " "Info: Total cell delay = 2.776 ns ( 41.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.848 ns ( 58.09 % ) " "Info: Total interconnect delay = 3.848 ns ( 58.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.624 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp5[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.624 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} pinlvji:inst1|cntp5[3] {} } { 0.000ns 0.000ns 1.559ns 1.473ns 0.816ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.624 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.624 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypinlvji.bdf" "" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { { 64 -80 88 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.559 ns) + CELL(0.970 ns) 3.669 ns int_div:inst\|clk_tem 2 REG LCFF_X21_Y7_N13 2 " "Info: 2: + IC(1.559 ns) + CELL(0.970 ns) = 3.669 ns; Loc. = LCFF_X21_Y7_N13; Fanout = 2; REG Node = 'int_div:inst\|clk_tem'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.529 ns" { clk int_div:inst|clk_tem } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.473 ns) + CELL(0.000 ns) 5.142 ns int_div:inst\|clk_tem~clkctrl 3 COMB CLKCTRL_G5 64 " "Info: 3: + IC(1.473 ns) + CELL(0.000 ns) = 5.142 ns; Loc. = CLKCTRL_G5; Fanout = 64; COMB Node = 'int_div:inst\|clk_tem~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.666 ns) 6.624 ns pinlvji:inst1\|cntp5\[0\] 4 REG LCFF_X15_Y6_N27 6 " "Info: 4: + IC(0.816 ns) + CELL(0.666 ns) = 6.624 ns; Loc. = LCFF_X15_Y6_N27; Fanout = 6; REG Node = 'pinlvji:inst1\|cntp5\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.482 ns" { int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp5[0] } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 41.91 % ) " "Info: Total cell delay = 2.776 ns ( 41.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.848 ns ( 58.09 % ) " "Info: Total interconnect delay = 3.848 ns ( 58.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.624 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp5[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.624 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} pinlvji:inst1|cntp5[0] {} } { 0.000ns 0.000ns 1.559ns 1.473ns 0.816ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.624 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp5[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.624 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} pinlvji:inst1|cntp5[3] {} } { 0.000ns 0.000ns 1.559ns 1.473ns 0.816ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.624 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp5[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.624 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} pinlvji:inst1|cntp5[0] {} } { 0.000ns 0.000ns 1.559ns 1.473ns 0.816ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.385 ns" { pinlvji:inst1|cntp5[0] pinlvji:inst1|process1~256 pinlvji:inst1|process1~258 pinlvji:inst1|cntq1[3]~36 pinlvji:inst1|cntp6~468 pinlvji:inst1|cntp5~580 pinlvji:inst1|cntp5[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.385 ns" { pinlvji:inst1|cntp5[0] {} pinlvji:inst1|process1~256 {} pinlvji:inst1|process1~258 {} pinlvji:inst1|cntq1[3]~36 {} pinlvji:inst1|cntp6~468 {} pinlvji:inst1|cntp5~580 {} pinlvji:inst1|cntp5[3] {} } { 0.000ns 1.950ns 0.380ns 0.379ns 1.114ns 0.358ns 0.000ns } { 0.000ns 0.534ns 0.370ns 0.616ns 0.370ns 0.206ns 0.108ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.624 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp5[3] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.624 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} pinlvji:inst1|cntp5[3] {} } { 0.000ns 0.000ns 1.559ns 1.473ns 0.816ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.624 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp5[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.624 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} pinlvji:inst1|cntp5[0] {} } { 0.000ns 0.000ns 1.559ns 1.473ns 0.816ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 17 " "Warning: Circuit may not operate. Detected 17 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "pinlvji:inst1\|clk_cnt pinlvji:inst1\|cntp2\[0\] clk 1.511 ns " "Info: Found hold time violation between source  pin or register \"pinlvji:inst1\|clk_cnt\" and destination pin or register \"pinlvji:inst1\|cntp2\[0\]\" for clock \"clk\" (Hold time is 1.511 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.828 ns + Largest " "Info: + Largest clock skew is 3.828 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.632 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypinlvji.bdf" "" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { { 64 -80 88 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.559 ns) + CELL(0.970 ns) 3.669 ns int_div:inst\|clk_tem 2 REG LCFF_X21_Y7_N13 2 " "Info: 2: + IC(1.559 ns) + CELL(0.970 ns) = 3.669 ns; Loc. = LCFF_X21_Y7_N13; Fanout = 2; REG Node = 'int_div:inst\|clk_tem'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.529 ns" { clk int_div:inst|clk_tem } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.473 ns) + CELL(0.000 ns) 5.142 ns int_div:inst\|clk_tem~clkctrl 3 COMB CLKCTRL_G5 64 " "Info: 3: + IC(1.473 ns) + CELL(0.000 ns) = 5.142 ns; Loc. = CLKCTRL_G5; Fanout = 64; COMB Node = 'int_div:inst\|clk_tem~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl } "NODE_NAME" } } { "int_div.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/int_div.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.824 ns) + CELL(0.666 ns) 6.632 ns pinlvji:inst1\|cntp2\[0\] 4 REG LCFF_X17_Y7_N11 7 " "Info: 4: + IC(0.824 ns) + CELL(0.666 ns) = 6.632 ns; Loc. = LCFF_X17_Y7_N11; Fanout = 7; REG Node = 'pinlvji:inst1\|cntp2\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp2[0] } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 41.86 % ) " "Info: Total cell delay = 2.776 ns ( 41.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.856 ns ( 58.14 % ) " "Info: Total interconnect delay = 3.856 ns ( 58.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp2[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} pinlvji:inst1|cntp2[0] {} } { 0.000ns 0.000ns 1.559ns 1.473ns 0.824ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.804 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.804 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mypinlvji.bdf" "" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { { 64 -80 88 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 57 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 57; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "mypinlvji.bdf" "" { Schematic "E:/Altera/myvhdl/mypinlvji/mypinlvji.bdf" { { 64 -80 88 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.666 ns) 2.804 ns pinlvji:inst1\|clk_cnt 3 REG LCFF_X20_Y12_N17 24 " "Info: 3: + IC(0.855 ns) + CELL(0.666 ns) = 2.804 ns; Loc. = LCFF_X20_Y12_N17; Fanout = 24; REG Node = 'pinlvji:inst1\|clk_cnt'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.521 ns" { clk~clkctrl pinlvji:inst1|clk_cnt } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.41 % ) " "Info: Total cell delay = 1.806 ns ( 64.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 35.59 % ) " "Info: Total interconnect delay = 0.998 ns ( 35.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.804 ns" { clk clk~clkctrl pinlvji:inst1|clk_cnt } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.804 ns" { clk {} clk~combout {} clk~clkctrl {} pinlvji:inst1|clk_cnt {} } { 0.000ns 0.000ns 0.143ns 0.855ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp2[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} pinlvji:inst1|cntp2[0] {} } { 0.000ns 0.000ns 1.559ns 1.473ns 0.824ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.804 ns" { clk clk~clkctrl pinlvji:inst1|clk_cnt } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.804 ns" { clk {} clk~combout {} clk~clkctrl {} pinlvji:inst1|clk_cnt {} } { 0.000ns 0.000ns 0.143ns 0.855ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.319 ns - Shortest register register " "Info: - Shortest register to register delay is 2.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pinlvji:inst1\|clk_cnt 1 REG LCFF_X20_Y12_N17 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y12_N17; Fanout = 24; REG Node = 'pinlvji:inst1\|clk_cnt'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { pinlvji:inst1|clk_cnt } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.624 ns) 2.211 ns pinlvji:inst1\|cntp2\[0\]~400 2 COMB LCCOMB_X17_Y7_N10 1 " "Info: 2: + IC(1.587 ns) + CELL(0.624 ns) = 2.211 ns; Loc. = LCCOMB_X17_Y7_N10; Fanout = 1; COMB Node = 'pinlvji:inst1\|cntp2\[0\]~400'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.211 ns" { pinlvji:inst1|clk_cnt pinlvji:inst1|cntp2[0]~400 } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.319 ns pinlvji:inst1\|cntp2\[0\] 3 REG LCFF_X17_Y7_N11 7 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.319 ns; Loc. = LCFF_X17_Y7_N11; Fanout = 7; REG Node = 'pinlvji:inst1\|cntp2\[0\]'" {  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { pinlvji:inst1|cntp2[0]~400 pinlvji:inst1|cntp2[0] } "NODE_NAME" } } { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.732 ns ( 31.57 % ) " "Info: Total cell delay = 0.732 ns ( 31.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.587 ns ( 68.43 % ) " "Info: Total interconnect delay = 1.587 ns ( 68.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { pinlvji:inst1|clk_cnt pinlvji:inst1|cntp2[0]~400 pinlvji:inst1|cntp2[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.319 ns" { pinlvji:inst1|clk_cnt {} pinlvji:inst1|cntp2[0]~400 {} pinlvji:inst1|cntp2[0] {} } { 0.000ns 1.587ns 0.000ns } { 0.000ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "pinlvji.vhd" "" { Text "E:/Altera/myvhdl/mypinlvji/pinlvji.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.632 ns" { clk int_div:inst|clk_tem int_div:inst|clk_tem~clkctrl pinlvji:inst1|cntp2[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "6.632 ns" { clk {} clk~combout {} int_div:inst|clk_tem {} int_div:inst|clk_tem~clkctrl {} pinlvji:inst1|cntp2[0] {} } { 0.000ns 0.000ns 1.559ns 1.473ns 0.824ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.804 ns" { clk clk~clkctrl pinlvji:inst1|clk_cnt } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.804 ns" { clk {} clk~combout {} clk~clkctrl {} pinlvji:inst1|clk_cnt {} } { 0.000ns 0.000ns 0.143ns 0.855ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { pinlvji:inst1|clk_cnt pinlvji:inst1|cntp2[0]~400 pinlvji:inst1|cntp2[0] } "NODE_NAME" } } { "e:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/quartus/bin/Technology_Viewer.qrui" "2.319 ns" { pinlvji:inst1|clk_cnt {} pinlvji:inst1|cntp2[0]~400 {} pinlvji:inst1|cntp2[0] {} } { 0.000ns 1.587ns 0.000ns } { 0.000ns 0.624ns 0.108ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}