elock.rpt

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-- Equation name is '_LC7_B2', type is buried 
_LC7_B2  = LCELL( _EQ015);
  _EQ015 = !_LC3_B6 &  _LC4_B2
         #  _LC2_B2 &  _LC6_B2;

-- Node name is '~789~1' 
-- Equation name is '~789~1', location is LC6_B2, type is buried.
-- synthesized logic cell 
_LC6_B2  = LCELL( _EQ016);
  _EQ016 =  k11 &  _LC3_B6
         #  _LC3_B6 &  _LC3_B9;

-- Node name is ':791' 
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = LCELL( _EQ017);
  _EQ017 = !_LC1_B6 &  _LC7_B2
         #  _LC1_B4 &  _LC2_B2;

-- Node name is '~792~1' 
-- Equation name is '~792~1', location is LC1_B4, type is buried.
-- synthesized logic cell 
_LC1_B4  = LCELL( _EQ018);
  _EQ018 =  k22 &  _LC1_B6
         #  _LC1_B6 &  _LC3_B9;

-- Node name is ':794' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = LCELL( _EQ019);
  _EQ019 = !_LC2_B6 &  _LC8_B2
         #  _LC2_B2 &  _LC8_B10;

-- Node name is '~795~1' 
-- Equation name is '~795~1', location is LC8_B10, type is buried.
-- synthesized logic cell 
_LC8_B10 = LCELL( _EQ020);
  _EQ020 =  k33 &  _LC2_B6
         #  _LC2_B6 &  _LC3_B9;

-- Node name is '~814~1' 
-- Equation name is '~814~1', location is LC5_B2, type is buried.
-- synthesized logic cell 
_LC5_B2  = LCELL( _EQ021);
  _EQ021 =  _LC3_B2 & !_LC3_B6
         #  k11 &  _LC3_B6
         #  _LC3_B6 &  _LC3_B9;

-- Node name is '~814~2' 
-- Equation name is '~814~2', location is LC1_B7, type is buried.
-- synthesized logic cell 
_LC1_B7  = LCELL( _EQ022);
  _EQ022 =  _LC1_B4 & !_LC2_B6
         # !_LC1_B6 & !_LC2_B6 &  _LC5_B2;

-- Node name is ':814' 
-- Equation name is '_LC3_B7', type is buried 
_LC3_B7  = LCELL( _EQ023);
  _EQ023 = !k1010
         #  _LC1_B7 &  _LC3_B7
         #  _LC3_B7 &  _LC8_B10;

-- Node name is '~820~1' 
-- Equation name is '~820~1', location is LC4_B7, type is buried.
-- synthesized logic cell 
_LC4_B7  = LCELL( _EQ024);
  _EQ024 =  _LC1_B6
         #  _LC2_B6
         #  _LC5_B2;

-- Node name is '~820~2' 
-- Equation name is '~820~2', location is LC7_B7, type is buried.
-- synthesized logic cell 
_LC7_B7  = LCELL( _EQ025);
  _EQ025 = !k33 &  _LC2_B6 & !_LC3_B9
         #  _LC5_B7;

-- Node name is ':820' 
-- Equation name is '_LC8_B7', type is buried 
_LC8_B7  = LCELL( _EQ026);
  _EQ026 =  k1010 &  _LC4_B7 &  _LC8_B7
         #  k1010 &  _LC7_B7;

-- Node name is '~826~1' 
-- Equation name is '~826~1', location is LC5_B6, type is buried.
-- synthesized logic cell 
_LC5_B6  = LCELL( _EQ027);
  _EQ027 =  _LC4_B6
         # !k33 & !_LC3_B9;

-- Node name is '~826~2' 
-- Equation name is '~826~2', location is LC1_B2, type is buried.
-- synthesized logic cell 
_LC1_B2  = LCELL( _EQ028);
  _EQ028 =  _LC3_B2 &  _LC4_B6
         #  _LC3_B6 &  _LC4_B6
         #  _LC2_B11 &  _LC3_B6;

-- Node name is '~826~3' 
-- Equation name is '~826~3', location is LC6_B6, type is buried.
-- synthesized logic cell 
_LC6_B6  = LCELL( _EQ029);
  _EQ029 =  _LC1_B2 & !_LC1_B6
         #  _LC1_B4 &  _LC4_B6;

-- Node name is ':826' 
-- Equation name is '_LC4_B6', type is buried 
_LC4_B6  = LCELL( _EQ030);
  _EQ030 =  k1010 &  _LC2_B6 &  _LC5_B6
         #  k1010 &  _LC6_B6;

-- Node name is '~924~1' 
-- Equation name is '~924~1', location is LC7_B10, type is buried.
-- synthesized logic cell 
!_LC7_B10 = _LC7_B10~NOT;
_LC7_B10~NOT = LCELL( _EQ031);
  _EQ031 =  k44 &  k55 &  k77 &  k88;

-- Node name is '~924~2' 
-- Equation name is '~924~2', location is LC6_B11, type is buried.
-- synthesized logic cell 
!_LC6_B11 = _LC6_B11~NOT;
_LC6_B11~NOT = LCELL( _EQ032);
  _EQ032 =  k11 &  k22 &  k66 &  k99;

-- Node name is ':925' 
-- Equation name is '_LC4_B10', type is buried 
!_LC4_B10 = _LC4_B10~NOT;
_LC4_B10~NOT = LCELL( _EQ033);
  _EQ033 =  k33 & !_LC6_B11 & !_LC7_B10
         #  _LC3_B9;

-- Node name is ':1005' 
-- Equation name is '_LC2_B8', type is buried 
_LC2_B8  = LCELL( _EQ034);
  _EQ034 =  count10 &  count11 &  _LC4_B10;

-- Node name is '~1025~1' 
-- Equation name is '~1025~1', location is LC6_B8, type is buried.
-- synthesized logic cell 
_LC6_B8  = LCELL( _EQ035);
  _EQ035 =  count10 & !count11 &  _LC4_B10
         # !count10 &  count11
         #  count11 & !_LC4_B10;

-- Node name is ':1099' 
-- Equation name is '_LC3_B9', type is buried 
_LC3_B9  = LCELL( _EQ036);
  _EQ036 =  count13
         #  count12;

-- Node name is ':1269' 
-- Equation name is '_LC5_B9', type is buried 
_LC5_B9  = LCELL( _EQ037);
  _EQ037 = !count10 &  count13
         # !count11 &  count13
         # !count10 &  count11
         #  count11 & !count13
         # !count12 &  count13
         #  count10 & !count11 &  count12
         #  count10 &  count12 & !count13
         # !count10 & !count12
         #  count11 & !count12;

-- Node name is ':1303' 
-- Equation name is '_LC6_B9', type is buried 
_LC6_B9  = LCELL( _EQ038);
  _EQ038 = !count12
         #  count10 &  count11
         # !count10 & !count11
         #  count10 &  count13
         # !count11 &  count13;

-- Node name is ':1339' 
-- Equation name is '_LC1_B9', type is buried 
_LC1_B9  = LCELL( _EQ039);
  _EQ039 =  count10
         # !count11
         #  count12 & !count13
         # !count12 &  count13;

-- Node name is ':1377' 
-- Equation name is '_LC7_B9', type is buried 
_LC7_B9  = LCELL( _EQ040);
  _EQ040 = !count10 &  count13
         # !count10 &  count11
         # !count11 &  count13
         # !count12 &  count13
         # !count10 & !count12
         #  count11 & !count12
         #  count10 & !count11 &  count12;

-- Node name is ':1413' 
-- Equation name is '_LC8_B9', type is buried 
_LC8_B9  = LCELL( _EQ041);
  _EQ041 =  count12 &  count13
         #  count11 &  count13
         # !count10 &  count13
         # !count10 & !count12
         # !count10 &  count11;

-- Node name is ':1449' 
-- Equation name is '_LC2_B9', type is buried 
_LC2_B9  = LCELL( _EQ042);
  _EQ042 =  count13
         # !count10 &  count12
         # !count11 &  count12
         # !count10 & !count11;

-- Node name is ':1485' 
-- Equation name is '_LC4_B9', type is buried 
_LC4_B9  = LCELL( _EQ043);
  _EQ043 = !count10 &  count12 & !count13
         # !count11 &  count12 & !count13
         # !count10 &  count11 & !count13
         #  count11 & !count12 & !count13
         # !count10 &  count11 &  count12
         #  count11 &  count12 &  count13
         # !count11 & !count12 &  count13;



Project Information                     d:\program files\myeda\elock\elock.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:03
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:02
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:10


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,659K