📄 elock.rpt
字号:
- 3 - B 02 OR2 s 0 3 0 2 ~719~1
- 3 - B 06 AND2 0 3 0 4 :726
- 1 - B 06 OR2 ! 0 3 0 6 :736
- 5 - B 07 AND2 s 0 4 0 1 ~746~1
- 2 - B 11 AND2 s 0 3 0 1 ~746~2
- 2 - B 06 AND2 0 3 0 8 :746
- 4 - B 02 OR2 0 4 0 1 :785
- 7 - B 02 OR2 0 4 0 1 :788
- 6 - B 02 OR2 s 0 3 0 1 ~789~1
- 8 - B 02 OR2 0 4 0 1 :791
- 1 - B 04 OR2 s 0 3 0 3 ~792~1
- 2 - B 02 OR2 0 3 0 7 :794
- 8 - B 10 OR2 s 0 3 0 2 ~795~1
- 5 - B 02 OR2 s 0 4 0 2 ~814~1
- 1 - B 07 OR2 s 0 4 0 1 ~814~2
- 3 - B 07 OR2 0 3 0 1 :814
- 4 - B 07 OR2 s 0 3 0 1 ~820~1
- 7 - B 07 OR2 s 0 4 0 1 ~820~2
- 8 - B 07 OR2 0 3 0 1 :820
- 5 - B 06 OR2 s 0 3 0 1 ~826~1
- 1 - B 02 OR2 s 0 4 0 1 ~826~2
- 6 - B 06 OR2 s 0 4 0 1 ~826~3
- 4 - B 06 OR2 0 4 0 4 :826
- 7 - B 10 AND2 s ! 0 4 0 1 ~924~1
- 6 - B 11 AND2 s ! 0 4 0 1 ~924~2
- 4 - B 10 OR2 ! 0 4 0 3 :925
- 2 - B 08 AND2 0 3 0 1 :1005
- 6 - B 08 OR2 s 0 3 0 1 ~1025~1
- 3 - B 09 OR2 0 2 0 11 :1099
- 5 - B 09 OR2 0 4 1 0 :1269
- 6 - B 09 OR2 0 4 1 0 :1303
- 1 - B 09 OR2 0 4 1 0 :1339
- 7 - B 09 OR2 0 4 1 0 :1377
- 8 - B 09 OR2 0 4 1 0 :1413
- 2 - B 09 OR2 0 4 1 0 :1449
- 4 - B 09 OR2 0 4 1 0 :1485
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\program files\myeda\elock\elock.rpt
elock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 10/ 96( 10%) 28/ 48( 58%) 0/ 48( 0%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\program files\myeda\elock\elock.rpt
elock
** CLOCK SIGNALS **
Type Fan-out Name
DFF 17 carry
INPUT 3 clk
Device-Specific Information: d:\program files\myeda\elock\elock.rpt
elock
** EQUATIONS **
clk : INPUT;
k1 : INPUT;
k2 : INPUT;
k3 : INPUT;
k4 : INPUT;
k5 : INPUT;
k6 : INPUT;
k7 : INPUT;
k8 : INPUT;
k9 : INPUT;
k10 : INPUT;
-- Node name is ':25' = 'carry'
-- Equation name is 'carry', location is LC7_B11, type is buried.
carry = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = count0 & count1;
-- Node name is ':24' = 'count0'
-- Equation name is 'count0', location is LC4_B11, type is buried.
count0 = DFFE(!count0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':23' = 'count1'
-- Equation name is 'count1', location is LC1_B11, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = count0 & !count1
# !count0 & count1;
-- Node name is ':47' = 'count10'
-- Equation name is 'count10', location is LC5_B8, type is buried.
count10 = DFFE( _EQ003, carry, VCC, VCC, VCC);
_EQ003 = !count10 & k1010 & _LC4_B10
# count10 & k1010 & !_LC4_B10
# k1010 & _LC2_B2;
-- Node name is ':46' = 'count11'
-- Equation name is 'count11', location is LC1_B8, type is buried.
count11 = DFFE( _EQ004, carry, VCC, VCC, VCC);
_EQ004 = k1010 & _LC6_B8
# k1010 & _LC2_B2;
-- Node name is ':45' = 'count12'
-- Equation name is 'count12', location is LC8_B8, type is buried.
count12 = DFFE( _EQ005, carry, VCC, VCC, VCC);
_EQ005 = count12 & k1010
# k1010 & _LC2_B8
# k1010 & _LC2_B2;
-- Node name is ':44' = 'count13'
-- Equation name is 'count13', location is LC4_B8, type is buried.
count13 = DFFE( _EQ006, carry, VCC, VCC, VCC);
_EQ006 = count13 & k1010
# k1010 & _LC2_B2;
-- Node name is ':26' = 'k11'
-- Equation name is 'k11', location is LC3_B11, type is buried.
k11 = DFFE( k1, carry, VCC, VCC, VCC);
-- Node name is ':27' = 'k22'
-- Equation name is 'k22', location is LC5_B4, type is buried.
k22 = DFFE( k2, carry, VCC, VCC, VCC);
-- Node name is ':28' = 'k33'
-- Equation name is 'k33', location is LC1_B10, type is buried.
k33 = DFFE( k3, carry, VCC, VCC, VCC);
-- Node name is ':29' = 'k44'
-- Equation name is 'k44', location is LC2_B10, type is buried.
k44 = DFFE( k4, carry, VCC, VCC, VCC);
-- Node name is ':30' = 'k55'
-- Equation name is 'k55', location is LC3_B10, type is buried.
k55 = DFFE( k5, carry, VCC, VCC, VCC);
-- Node name is ':31' = 'k66'
-- Equation name is 'k66', location is LC2_B4, type is buried.
k66 = DFFE( k6, carry, VCC, VCC, VCC);
-- Node name is ':32' = 'k77'
-- Equation name is 'k77', location is LC5_B10, type is buried.
k77 = DFFE( k7, carry, VCC, VCC, VCC);
-- Node name is ':33' = 'k88'
-- Equation name is 'k88', location is LC6_B10, type is buried.
k88 = DFFE( k8, carry, VCC, VCC, VCC);
-- Node name is ':34' = 'k99'
-- Equation name is 'k99', location is LC5_B11, type is buried.
k99 = DFFE( k9, carry, VCC, VCC, VCC);
-- Node name is ':35' = 'k1010'
-- Equation name is 'k1010', location is LC3_B8, type is buried.
k1010 = DFFE( k10, carry, VCC, VCC, VCC);
-- Node name is 'led0'
-- Equation name is 'led0', type is output
led0 = GND;
-- Node name is 'led1'
-- Equation name is 'led1', type is output
led1 = _LC4_B9;
-- Node name is 'led2'
-- Equation name is 'led2', type is output
led2 = _LC2_B9;
-- Node name is 'led3'
-- Equation name is 'led3', type is output
led3 = _LC8_B9;
-- Node name is 'led4'
-- Equation name is 'led4', type is output
led4 = _LC7_B9;
-- Node name is 'led5'
-- Equation name is 'led5', type is output
led5 = _LC1_B9;
-- Node name is 'led6'
-- Equation name is 'led6', type is output
led6 = _LC6_B9;
-- Node name is 'led7'
-- Equation name is 'led7', type is output
led7 = _LC5_B9;
-- Node name is 'row0'
-- Equation name is 'row0', type is output
row0 = VCC;
-- Node name is 'row1'
-- Equation name is 'row1', type is output
row1 = GND;
-- Node name is 'row2'
-- Equation name is 'row2', type is output
row2 = VCC;
-- Node name is ':41' = 'state0'
-- Equation name is 'state0', location is LC7_B6, type is buried.
state0 = DFFE( _LC4_B6, carry, VCC, VCC, VCC);
-- Node name is ':40' = 'state1'
-- Equation name is 'state1', location is LC6_B7, type is buried.
state1 = DFFE( _LC8_B7, carry, VCC, VCC, VCC);
-- Node name is ':39' = 'state2'
-- Equation name is 'state2', location is LC2_B7, type is buried.
state2 = DFFE( _LC3_B7, carry, VCC, VCC, VCC);
-- Node name is ':716'
-- Equation name is '_LC8_B6', type is buried
!_LC8_B6 = _LC8_B6~NOT;
_LC8_B6~NOT = LCELL( _EQ007);
_EQ007 = state1
# !state0
# state2;
-- Node name is '~719~1'
-- Equation name is '~719~1', location is LC3_B2, type is buried.
-- synthesized logic cell
_LC3_B2 = LCELL( _EQ008);
_EQ008 = !_LC8_B6
# k66
# _LC3_B9;
-- Node name is ':726'
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = LCELL( _EQ009);
_EQ009 = !state0 & state1 & !state2;
-- Node name is ':736'
-- Equation name is '_LC1_B6', type is buried
!_LC1_B6 = _LC1_B6~NOT;
_LC1_B6~NOT = LCELL( _EQ010);
_EQ010 = !state1
# !state0
# state2;
-- Node name is '~746~1'
-- Equation name is '~746~1', location is LC5_B7, type is buried.
-- synthesized logic cell
_LC5_B7 = LCELL( _EQ011);
_EQ011 = !k22 & _LC1_B6 & !_LC2_B6 & !_LC3_B9;
-- Node name is '~746~2'
-- Equation name is '~746~2', location is LC2_B11, type is buried.
-- synthesized logic cell
_LC2_B11 = LCELL( _EQ012);
_EQ012 = !k11 & !_LC2_B6 & !_LC3_B9;
-- Node name is ':746'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ013);
_EQ013 = !state0 & !state1 & state2;
-- Node name is ':785'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = LCELL( _EQ014);
_EQ014 = k66 & _LC2_B2
# _LC2_B2 & _LC3_B9
# !_LC8_B6;
-- Node name is ':788'
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