📄 w429.vhd
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--程序功能：按照输入的地址保存输入的数据，把保存的数据按照输入的时钟频率
-- 以429总线形式串行发送出去。具有片选和复位功能。
-- 地址为：0000 0000 保存的数为间隙周期。
-- 地址为：0000 0001~0100 0000 保存需要发送的数据共32组32位（64组16位）。
-- 可以单次发送，也可以循环发送。
--不足之处：加法器的进位没考虑，没有使用内存，而是大量使用了寄存器，占用76%的CELL
-- 要改用内存描述。
--修改记录：2007年12月13日由徐志兵创建。没有很好考虑间隙周期太大进位问题，直接去了。
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity w429 is
port(
reset : in std_logic;--复位信号
clk : in std_logic;--输入时钟 2*12.5k 或 2*48k 或 2*100k
cs : in std_logic;--片选信号
data_in : in std_logic_vector(15 downto 0);--数据总线
start : in std_logic;--开始发送
addr : in std_logic_vector(7 downto 0);--地址输入
save : in std_logic;--保存需发送的数据
repeat : in std_logic;--高电平循环发送第一组数据低电平单次发送32组数据
txA : out std_logic;--429输出正端
txB : out std_logic;--429输出负端
space : out std_logic;--输出间隙周期指示
half_out : out std_logic--单次发送时当输出一半数据时给高电平
);
end w429;
architecture a of w429 is
signal data_reg0 : std_logic_vector(31 downto 0);--存放间隙周期数
signal data_reg1 : std_logic_vector(31 downto 0);--存放第一组数据
signal data_reg2 : std_logic_vector(31 downto 0);
signal data_reg3 : std_logic_vector(31 downto 0);
signal data_reg4 : std_logic_vector(31 downto 0);
signal data_reg5 : std_logic_vector(31 downto 0);
signal data_reg6 : std_logic_vector(31 downto 0);
signal data_reg7 : std_logic_vector(31 downto 0);
signal data_reg8 : std_logic_vector(31 downto 0);
signal data_reg9 : std_logic_vector(31 downto 0);
signal data_reg10 : std_logic_vector(31 downto 0);
signal data_reg11 : std_logic_vector(31 downto 0);
signal data_reg12 : std_logic_vector(31 downto 0);
signal data_reg13 : std_logic_vector(31 downto 0);
signal data_reg14 : std_logic_vector(31 downto 0);
signal data_reg15 : std_logic_vector(31 downto 0);
signal data_reg16 : std_logic_vector(31 downto 0);
signal data_reg17 : std_logic_vector(31 downto 0);
signal data_reg18 : std_logic_vector(31 downto 0);
signal data_reg19 : std_logic_vector(31 downto 0);
signal data_reg20 : std_logic_vector(31 downto 0);
signal data_reg21 : std_logic_vector(31 downto 0);
signal data_reg22 : std_logic_vector(31 downto 0);
signal data_reg23 : std_logic_vector(31 downto 0);
signal data_reg24 : std_logic_vector(31 downto 0);
signal data_reg25 : std_logic_vector(31 downto 0);
signal data_reg26 : std_logic_vector(31 downto 0);
signal data_reg27 : std_logic_vector(31 downto 0);
signal data_reg28 : std_logic_vector(31 downto 0);
signal data_reg29 : std_logic_vector(31 downto 0);
signal data_reg30 : std_logic_vector(31 downto 0);
signal data_reg31 : std_logic_vector(31 downto 0);
signal data_reg32 : std_logic_vector(31 downto 0);--存放第32组数据
signal data_count1 : std_logic_vector(31 downto 0);--循环数据发送计数器
signal data_count1_ref : std_logic_vector(31 downto 0);--数据发送参考计数器
signal data_count2_ref : std_logic_vector(31 downto 0);
signal data_count3_ref : std_logic_vector(31 downto 0);
signal data_count4_ref : std_logic_vector(31 downto 0);
signal data_count5_ref : std_logic_vector(31 downto 0);
signal data_count6_ref : std_logic_vector(31 downto 0);
signal data_count7_ref : std_logic_vector(31 downto 0);
signal data_count8_ref : std_logic_vector(31 downto 0);
signal data_count9_ref : std_logic_vector(31 downto 0);
signal data_count10_ref : std_logic_vector(31 downto 0);
signal data_count20_ref : std_logic_vector(31 downto 0);
signal data_count30_ref : std_logic_vector(31 downto 0);
signal data_count2 : std_logic_vector(31 downto 0);--单次组数据发送计数器
signal data_count3 : std_logic_vector(31 downto 0);--帧发送计数器
signal datafifo2 : std_logic_vector(31 downto 0);--单次发送的组数据
signal outputa : std_logic;
signal outputb : std_logic;
signal outputc : std_logic;
signal outputd : std_logic;
signal space1 : std_logic;
signal space2 : std_logic;
function JIA (A,B : std_logic_vector)--任意位矢量全加器,舍弃了进位端
return std_logic_vector is
variable LV : std_logic_vector(A'Length-1 downto 0);
variable RV : std_logic_vector(B'Length-1 downto 0);
variable Result : std_logic_vector(A'Length-1 downto 0);
variable Carry : std_logic := '0';
begin
LV := A;
RV := B;
assert A'Length =B'Length
report "function JIA : operands have different widths"
severity Failure;
for I in Result'Reverse_range loop
Result(I) := LV(I) xor RV(I) xor Carry;
Carry := (LV(I) and RV(I)) or (LV(I) and Carry) or (RV(I) and Carry);
end loop;
return Result;
end JIA;
begin
process(data_in,save,addr,cs)--存储33组32位数据，先低16位，后高16位
begin
if cs = '1' then--片选有效
if reset = '0' then--复位无效
if save = '1' then--存储指令有效
if addr = "00000000" then--存放间隙周期的低16位数据
data_reg0(15 downto 0) <= data_in;
end if;
if addr = "00000001" then--存放间隙周期的高16位数据
data_reg0(31 downto 16) <= data_in;
end if;
if addr = "00000010" then--存放第一组数据的低16位
data_reg1(15 downto 0) <= data_in;
end if;
if addr = "00000011" then--存放第一组数据的高16位
data_reg1(31 downto 16) <= data_in;
end if;
if addr = "00000100" then
data_reg2(15 downto 0) <= data_in;
end if;
if addr = "00000101" then
data_reg2(31 downto 16) <= data_in;
end if;
if addr = "00000110" then
data_reg3(15 downto 0) <= data_in;
end if;
if addr = "00000111" then
data_reg3(31 downto 16) <= data_in;
end if;
if addr = "00001000" then
data_reg4(15 downto 0) <= data_in;
end if;
if addr = "00001001" then
data_reg4(31 downto 16) <= data_in;
end if;
if addr = "00001010" then
data_reg5(15 downto 0) <= data_in;
end if;
if addr = "00001011" then
data_reg5(31 downto 16) <= data_in;
end if;
if addr = "00001100" then
data_reg6(15 downto 0) <= data_in;
end if;
if addr = "00001101" then
data_reg6(31 downto 16) <= data_in;
end if;
if addr = "00001110" then
data_reg7(15 downto 0) <= data_in;
end if;
if addr = "00001111" then
data_reg7(31 downto 16) <= data_in;
end if;
if addr = "00010000" then
data_reg8(15 downto 0) <= data_in;
end if;
if addr = "00010001" then
data_reg8(31 downto 16) <= data_in;
end if;
if addr = "00010010" then
data_reg9(15 downto 0) <= data_in;
end if;
if addr = "00010011" then
data_reg9(31 downto 16) <= data_in;
end if;
if addr = "00010100" then
data_reg10(15 downto 0) <= data_in;
end if;
if addr = "00010101" then
data_reg10(31 downto 16) <= data_in;
end if;
if addr = "00010110" then
data_reg11(15 downto 0) <= data_in;
end if;
if addr = "00010111" then
data_reg11(31 downto 16) <= data_in;
end if;
if addr = "00011000" then
data_reg12(15 downto 0) <= data_in;
end if;
if addr = "00011001" then
data_reg12(31 downto 16) <= data_in;
end if;
if addr = "00011010" then
data_reg13(15 downto 0) <= data_in;
end if;
if addr = "00011011" then
data_reg13(31 downto 16) <= data_in;
end if;
if addr = "00011100" then
data_reg14(15 downto 0) <= data_in;
end if;
if addr = "00011101" then
data_reg14(31 downto 16) <= data_in;
end if;
if addr = "00011110" then
data_reg15(15 downto 0) <= data_in;
end if;
if addr = "00011111" then
data_reg15(31 downto 16) <= data_in;
end if;
if addr = "00100000" then
data_reg16(15 downto 0) <= data_in;
end if;
if addr = "00100001" then
data_reg16(31 downto 16) <= data_in;
end if;
if addr = "00100010" then
data_reg17(15 downto 0) <= data_in;
end if;
if addr = "00100011" then
data_reg17(31 downto 16) <= data_in;
end if;
if addr = "00100100" then
data_reg18(15 downto 0) <= data_in;
end if;
if addr = "00100101" then
data_reg18(31 downto 16) <= data_in;
end if;
if addr = "00100110" then
data_reg19(15 downto 0) <= data_in;
end if;
if addr = "00100111" then
data_reg19(31 downto 16) <= data_in;
end if;
if addr = "00101000" then
data_reg20(15 downto 0) <= data_in;
end if;
if addr = "00101001" then
data_reg20(31 downto 16) <= data_in;
end if;
if addr = "00101010" then
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