📄 s429.vhd
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--模块功能：输入5M时钟，分频产生2*12.5k 或 2*48k 或 2*100k 或2*250k
-- 通过间歇寄存器的高2位控制频率大小，在该频率下把并口的数据串行输出，
-- 每个数据之间插入设置的间歇周期
--模块接口：5M时钟输入，片选，复位，存储，开始，地址，平行数据输入，
-- 输出串行码，间歇周期，内部寄存器发送过半指示。
--其他说明：2008年3月14日由徐志兵创建，由于48K频率不太好分频，鉴于它有25%的频偏设成50K
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity s429 is
port(
clk5m : in std_logic;--5M时钟输入
cs : in std_logic;--片选信号
reset : in std_logic;--复位信号
start : in std_logic;--开始发送
save : in std_logic;--保存数据
addr : in std_logic_vector(3 downto 0);--保存需要发送的数据和间歇周期以及时钟选择的地址
pdata : in std_logic_vector(15 downto 0);--数据输入
outputa : out std_logic;--429输出正端
outputb : out std_logic;--429输出负端
half_reg : out std_logic;--内部寄存器发送过半指示
-- clk25k1 : out std_logic;
-- clk100k1 : out std_logic;
-- clk200k1 : out std_logic;
-- clk500k1 : out std_logic;
-- difcount : out std_logic_vector(7 downto 0);
space : out std_logic--输出间歇周期指示
);
end s429;
architecture a of s429 is
signal space_reg : std_logic_vector(15 downto 0);--存放间歇周期数，高2位为时钟选择用
signal data_reg1 : std_logic_vector(31 downto 0);--存放第一组数据
signal data_reg2 : std_logic_vector(31 downto 0);--存放第二组数据
signal data_reg3 : std_logic_vector(31 downto 0);--存放第三组数据
signal data_reg4 : std_logic_vector(31 downto 0);--存放第四组数据
signal data_fifo : std_logic_vector(31 downto 0);--数据发送FIFO
signal count_ref : std_logic_vector(15 downto 0);--加上间歇周期后需要发送的个数
signal count_send : std_logic_vector(15 downto 0);--帧发送计数器
signal trav_count : std_logic_vector(1 downto 0);--字发送计数器
signal divf_count1 : std_logic_vector(7 downto 0);--分频计数器
signal divf_count2 : std_logic_vector(5 downto 0);--分频计数器
signal divf_count3 : std_logic_vector(4 downto 0);--分频计数器
signal divf_count4 : std_logic_vector(3 downto 0);--分频计数器
signal clk : std_logic;--发送时钟
signal clk25k : std_logic;--外部可选的频率12.5k
signal clk100k : std_logic;--外部可选的频率50k
signal clk200k : std_logic;--外部可选的频率100k
signal clk500k : std_logic;--外部可选的频率250k
signal clk5md : std_logic;
begin
clk5md <= not clk5m;
process(clk5md,clk25k,clk100k,clk200k,clk500k,divf_count1)--分频25k,100k,200k,500k
begin
if falling_edge(clk5md) then
if divf_count1 = "11000111" then--25k,200分频11000111
divf_count1 <= "00000000";
clk25k <='0';
else
divf_count1 <= divf_count1+1;
clk25k <='1';
end if;
if divf_count2 = "110001" then--100k,50分频110001
divf_count2 <= "000000";
clk100k <='0';
else
divf_count2 <= divf_count2+1;
clk100k <='1';
end if;
if divf_count3 = "11000" then--200k,25分频11000
divf_count3 <= "00000";
clk200k <='0';
else
divf_count3 <= divf_count3+1;
clk200k <='1';
end if;
if divf_count4 = "1001" then--500k,10分频1001
divf_count4 <= "0000";
clk500k <='0';
else
divf_count4 <= divf_count4+1;
clk500k <='1';
end if;
end if;
end process;
process(space_reg(15 downto 14),clk25k,clk100k,clk200k,clk500k)
begin
if space_reg(15 downto 14)="00" then
clk<=clk25k;
elsif space_reg(15 downto 14)="01" then
clk<=clk100k;
elsif space_reg(15 downto 14)="10" then
clk<=clk200k;
else
clk<=clk500k;
end if;
end process;
count_ref <= ("00"&space_reg(13 downto 0))+("00"&space_reg(13 downto 0))+"1001000";--需发的帧数
process(save,addr,cs,reset,pdata)--向指定的地址存数据
begin
if cs = '1' then
-- if reset = '1' then
if save = '1' then
case addr is--一般初始状态都是0000，所以从1开始。
when "0001" => data_reg1(15 downto 0) <= pdata;
when "0010" => data_reg1(31 downto 16) <= pdata;
when "0011" => data_reg2(15 downto 0) <= pdata;
when "0100" => data_reg2(31 downto 16) <= pdata;
when "0101" => data_reg3(15 downto 0) <= pdata;
when "0110" => data_reg3(31 downto 16) <= pdata;
when "0111" => data_reg4(15 downto 0) <= pdata;
when "1000" => data_reg4(31 downto 16) <= pdata;
when "1001" => space_reg <= pdata;--设置间歇周期和发送频率
when others => null;
end case;
end if;
-- else
-- space_reg <= "0000000000000000";
-- data_reg1 <= "00000000000000000000000000000000";
-- data_reg2 <= "00000000000000000000000000000000";
-- data_reg3 <= "00000000000000000000000000000000";
-- data_reg4 <= "00000000000000000000000000000000";
-- end if;
end if;
end process;
process(cs,reset,start,count_ref,clk)--发送计数
begin
if cs='1' then
if reset='1' then
if start='1' then
if rising_edge(clk) then
if (count_send=count_ref-1) then
count_send <= "0000000000000000";
trav_count <= trav_count+1;
else
count_send <= count_send+1;
end if;
end if;
else
count_send <= count_ref-1;
trav_count <= "11";
end if;
else
count_send <= count_ref-1;
trav_count <= "11";
end if;
else
count_send <= count_ref-1;
trav_count <= "11";
end if;
end process;
process(trav_count,cs,reset,start,data_reg1,data_reg2,data_reg3,data_reg4)--选择需要发送的数据
begin
if cs='1' then
if reset='1' then
if start='1' then
case trav_count is
when "00" => data_fifo <= data_reg1;
half_reg <= '0';
when "01" => data_fifo <= data_reg2;
half_reg <= '0';
when "10" => data_fifo <= data_reg3;
half_reg <= '1';
when "11" => data_fifo <= data_reg4;
half_reg <= '1';
when others => null;
end case;
else
data_fifo <= "00000000000000000000000000000000";
half_reg <= '0';
end if;
else
data_fifo <= "00000000000000000000000000000000";
half_reg <= '0';
end if;
else
data_fifo <= "00000000000000000000000000000000";
half_reg <= '0';
end if;
end process;
process(count_send,data_fifo,cs,start)--32位帧发送，加上间歇周期
begin
if cs='1' then
if start='1' then
if count_send="0000000000000000" then
space <= '0';
end if;
if count_send="0000000001000000" then
space <= '1';
end if;
case count_send is
when "0000000000000000" => outputa<=data_fifo(0);outputb<=not data_fifo(0);
when "0000000000000001" => outputa<='0';outputb<='0';
when "0000000000000010" => outputa<=data_fifo(1);outputb<=not data_fifo(1);
when "0000000000000011" => outputa<='0';outputb<='0';
when "0000000000000100" => outputa<=data_fifo(2);outputb<=not data_fifo(2);
when "0000000000000101" => outputa<='0';outputb<='0';
when "0000000000000110" => outputa<=data_fifo(3);outputb<=not data_fifo(3);
when "0000000000000111" => outputa<='0';outputb<='0';
when "0000000000001000" => outputa<=data_fifo(4);outputb<=not data_fifo(4);
when "0000000000001001" => outputa<='0';outputb<='0';
when "0000000000001010" => outputa<=data_fifo(5);outputb<=not data_fifo(5);
when "0000000000001011" => outputa<='0';outputb<='0';
when "0000000000001100" => outputa<=data_fifo(6);outputb<=not data_fifo(6);
when "0000000000001101" => outputa<='0';outputb<='0';
when "0000000000001110" => outputa<=data_fifo(7);outputb<=not data_fifo(7);
when "0000000000001111" => outputa<='0';outputb<='0';
when "0000000000010000" => outputa<=data_fifo(8);outputb<=not data_fifo(8);
when "0000000000010001" => outputa<='0';outputb<='0';
when "0000000000010010" => outputa<=data_fifo(9);outputb<=not data_fifo(9);
when "0000000000010011" => outputa<='0';outputb<='0';
when "0000000000010100" => outputa<=data_fifo(10);outputb<=not data_fifo(10);
when "0000000000010101" => outputa<='0';outputb<='0';
when "0000000000010110" => outputa<=data_fifo(11);outputb<=not data_fifo(11);
when "0000000000010111" => outputa<='0';outputb<='0';
when "0000000000011000" => outputa<=data_fifo(12);outputb<=not data_fifo(12);
when "0000000000011001" => outputa<='0';outputb<='0';
when "0000000000011010" => outputa<=data_fifo(13);outputb<=not data_fifo(13);
when "0000000000011011" => outputa<='0';outputb<='0';
when "0000000000011100" => outputa<=data_fifo(14);outputb<=not data_fifo(14);
when "0000000000011101" => outputa<='0';outputb<='0';
when "0000000000011110" => outputa<=data_fifo(15);outputb<=not data_fifo(15);
when "0000000000011111" => outputa<='0';outputb<='0';
when "0000000000100000" => outputa<=data_fifo(16);outputb<=not data_fifo(16);
when "0000000000100001" => outputa<='0';outputb<='0';
when "0000000000100010" => outputa<=data_fifo(17);outputb<=not data_fifo(17);
when "0000000000100011" => outputa<='0';outputb<='0';
when "0000000000100100" => outputa<=data_fifo(18);outputb<=not data_fifo(18);
when "0000000000100101" => outputa<='0';outputb<='0';
when "0000000000100110" => outputa<=data_fifo(19);outputb<=not data_fifo(19);
when "0000000000100111" => outputa<='0';outputb<='0';
when "0000000000101000" => outputa<=data_fifo(20);outputb<=not data_fifo(20);
when "0000000000101001" => outputa<='0';outputb<='0';
when "0000000000101010" => outputa<=data_fifo(21);outputb<=not data_fifo(21);
when "0000000000101011" => outputa<='0';outputb<='0';
when "0000000000101100" => outputa<=data_fifo(22);outputb<=not data_fifo(22);
when "0000000000101101" => outputa<='0';outputb<='0';
when "0000000000101110" => outputa<=data_fifo(23);outputb<=not data_fifo(23);
when "0000000000101111" => outputa<='0';outputb<='0';
when "0000000000110000" => outputa<=data_fifo(24);outputb<=not data_fifo(24);
when "0000000000110001" => outputa<='0';outputb<='0';
when "0000000000110010" => outputa<=data_fifo(25);outputb<=not data_fifo(25);
when "0000000000110011" => outputa<='0';outputb<='0';
when "0000000000110100" => outputa<=data_fifo(26);outputb<=not data_fifo(26);
when "0000000000110101" => outputa<='0';outputb<='0';
when "0000000000110110" => outputa<=data_fifo(27);outputb<=not data_fifo(27);
when "0000000000110111" => outputa<='0';outputb<='0';
when "0000000000111000" => outputa<=data_fifo(28);outputb<=not data_fifo(28);
when "0000000000111001" => outputa<='0';outputb<='0';
when "0000000000111010" => outputa<=data_fifo(29);outputb<=not data_fifo(29);
when "0000000000111011" => outputa<='0';outputb<='0';
when "0000000000111100" => outputa<=data_fifo(30);outputb<=not data_fifo(30);
when "0000000000111101" => outputa<='0';outputb<='0';
when "0000000000111110" => outputa<=data_fifo(31);outputb<=not data_fifo(31);
when "0000000000111111" => outputa<='0';outputb<='0';
when "0000000001000000" => outputa<='0';outputb<='0';
when "0000000001000001" => outputa<='0';outputb<='0';
when "0000000001000010" => outputa<='0';outputb<='0';
when "0000000001000011" => outputa<='0';outputb<='0';
when "0000000001000100" => outputa<='0';outputb<='0';
when "0000000001000101" => outputa<='0';outputb<='0';
when "0000000001000110" => outputa<='0';outputb<='0';
when "0000000001000111" => outputa<='0';outputb<='0';
when others => outputa<='0';outputb<='0';
end case;
else
outputa<='0';outputb<='0';
space <= '0';
end if;
else
outputa<='0';outputb<='0';
space <= '0';
end if;
end process;
end a;⌨️ 快捷键说明
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