dport16.fit.qmsg

16位双向端口操作IP,对双向操作时很有用,希望有人喜欢!

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "process0~188 " "Info: The following pins have the same output enable: process0~188" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[0\] LVTTL " "Info: Type bidirectional pin dio\[0\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[0\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[0] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[1\] LVTTL " "Info: Type bidirectional pin dio\[1\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[1\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[1] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[2\] LVTTL " "Info: Type bidirectional pin dio\[2\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[2\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[2] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[3\] LVTTL " "Info: Type bidirectional pin dio\[3\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[3\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[3] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[4\] LVTTL " "Info: Type bidirectional pin dio\[4\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[4\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[4] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[5\] LVTTL " "Info: Type bidirectional pin dio\[5\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[5\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[5] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[6\] LVTTL " "Info: Type bidirectional pin dio\[6\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[6\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[6] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[7\] LVTTL " "Info: Type bidirectional pin dio\[7\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[7\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[7] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[8\] LVTTL " "Info: Type bidirectional pin dio\[8\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[8\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[8] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[9\] LVTTL " "Info: Type bidirectional pin dio\[9\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[9\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[9] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[10\] LVTTL " "Info: Type bidirectional pin dio\[10\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[10\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[10] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[11\] LVTTL " "Info: Type bidirectional pin dio\[11\] uses the LVTTL I/O standard" {  } { { "dport16.vhd" "" { Text "F:/graduate/dport16/dport16.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dio\[11\]" } } } } { "F:/graduate/dport16/db/dport16_cmp.qrpt" "" { Report "F:/graduate/dport16/db/dport16_cmp.qrpt" Compiler "dport16" "UNKNOWN" "V1" "F:/graduate/dport16/db/dport16.quartus_db" { Floorplan "F:/graduate/dport16/" "" "" { dio[11] } "NODE_NAME" } "" } } { "F:/graduate/dport16/dport16.fld" "" { Floorplan "F:/graduate/dport16/dport16.fld" "" "" { dio[11] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional dio\[12\] LVTTL " "Info: Type bidirectional pin dio\[