keys_test.map.rpt

4*8矩阵键盘的驱动程序。QuartusII5.0编译通过！

+-------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                 ;
+---------------------------------------------+---------------+
; Resource                                    ; Usage         ;
+---------------------------------------------+---------------+
; Total logic elements                        ; 76            ;
;     -- Combinational with no register       ; 38            ;
;     -- Register only                        ; 5             ;
;     -- Combinational with a register        ; 33            ;
;                                             ;               ;
; Logic element usage by number of LUT inputs ;               ;
;     -- 4 input functions                    ; 39            ;
;     -- 3 input functions                    ; 4             ;
;     -- 2 input functions                    ; 22            ;
;     -- 1 input functions                    ; 6             ;
;     -- 0 input functions                    ; 0             ;
;         -- Combinational cells for routing  ; 0             ;
;                                             ;               ;
; Logic elements by mode                      ;               ;
;     -- normal mode                          ; 66            ;
;     -- arithmetic mode                      ; 10            ;
;     -- qfbk mode                            ; 0             ;
;     -- register cascade mode                ; 0             ;
;     -- synchronous clear/load mode          ; 0             ;
;     -- asynchronous clear/load mode         ; 22            ;
;                                             ;               ;
; Total registers                             ; 38            ;
; Total logic cells in carry chains           ; 12            ;
; I/O pins                                    ; 24            ;
; Maximum fan-out node                        ; \counter:Q[0] ;
; Maximum fan-out                             ; 28            ;
; Total fan-out                               ; 314           ;
; Average fan-out                             ; 3.14          ;
+---------------------------------------------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                         ;
+--------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------+
; Compilation Hierarchy Node     ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                  ;
+--------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------+
; |keys_test                     ; 76 (48)     ; 38           ; 0           ; 24   ; 0            ; 38 (36)      ; 5 (0)             ; 33 (12)          ; 12 (7)          ; 0 (0)      ; |keys_test                           ;
;    |DEBOUNCING:\debounuing:U1| ; 9 (9)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; 4 (4)           ; 0 (0)      ; |keys_test|DEBOUNCING:\debounuing:U1 ;
;    |DEBOUNCING:\debounuing:U2| ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |keys_test|DEBOUNCING:\debounuing:U2 ;
;    |DEBOUNCING:\debounuing:U3| ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |keys_test|DEBOUNCING:\debounuing:U3 ;
;    |DEBOUNCING:\debounuing:U4| ; 9 (9)       ; 7            ; 0           ; 0    ; 0            ; 2 (2)        ; 2 (2)             ; 5 (5)            ; 1 (1)           ; 0 (0)      ; |keys_test|DEBOUNCING:\debounuing:U4 ;
+--------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 38    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 22    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 16    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 12:1               ; 2 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |keys_test|SEG~85          ;
; 13:1               ; 4 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |keys_test|SEG~84          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in G:/EDAV new/test_50/keys_test.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Jun 28 15:16:24 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keys_test -c keys_test
Warning: Can't analyze file -- file G:/EDAV new/test39/keys_test.vhd is missing
Info: Found 2 design units, including 1 entities, in source file DEBOUNCING.vhd
    Info: Found design unit 1: DEBOUNCING-a
    Info: Found entity 1: DEBOUNCING
Warning: Using design file keys_test.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: keys_test-a
    Info: Found entity 1: keys_test
Info: Elaborating entity "keys_test" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at keys_test.vhd(31): object "CLK_KEYBOARD" declared but not used
Info (10035): Verilog HDL or VHDL information at keys_test.vhd(47): object "S" declared but not used
Info: Elaborating entity "DEBOUNCING" for hierarchy "DEBOUNCING:\debounuing:U1"
Warning (10492): VHDL Process Statement warning at DEBOUNCING.vhd(68): signal "d0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at DEBOUNCING.vhd(68): signal "d1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Duplicate registers merged to single register
    Info: Duplicate register "DEBOUNCING:\debounuing:U1|\free_counter:QQ[4]" merged to single register "DEBOUNCING:\debounuing:U4|\free_counter:QQ[4]"
    Info: Duplicate register "DEBOUNCING:\debounuing:U2|\free_counter:QQ[4]" merged to single register "DEBOUNCING:\debounuing:U4|\free_counter:QQ[4]"
    Info: Duplicate register "DEBOUNCING:\debounuing:U3|\free_counter:QQ[4]" merged to single register "DEBOUNCING:\debounuing:U4|\free_counter:QQ[4]"
    Info: Duplicate register "DEBOUNCING:\debounuing:U1|\free_counter:d0" merged to single register "DEBOUNCING:\debounuing:U4|\free_counter:d0"
    Info: Duplicate register "DEBOUNCING:\debounuing:U2|\free_counter:d0" merged to single register "DEBOUNCING:\debounuing:U4|\free_counter:d0"
    Info: Duplicate register "DEBOUNCING:\debounuing:U3|\free_counter:d0" merged to single register "DEBOUNCING:\debounuing:U4|\free_counter:d0"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "BCD_CODE[5]" stuck at GND
    Warning: Pin "BCD_CODE[6]" stuck at GND
    Warning: Pin "BCD_CODE[7]" stuck at GND
Info: Implemented 100 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 18 output pins
    Info: Implemented 76 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Processing ended: Wed Jun 28 15:16:34 2006
    Info: Elapsed time: 00:00:12