keys_test.map.qmsg

来自「4*8矩阵键盘的驱动程序。QuartusII5.0编译通过！」· QMSG 代码 · 共 17 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 28 15:16:24 2006 " "Info: Processing started: Wed Jun 28 15:16:24 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off keys_test -c keys_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keys_test -c keys_test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/EDAV new/test39/keys_test.vhd " "Warning: Can't analyze file -- file G:/EDAV new/test39/keys_test.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DEBOUNCING.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DEBOUNCING.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DEBOUNCING-a " "Info: Found design unit 1: DEBOUNCING-a" {  } { { "DEBOUNCING.vhd" "" { Text "G:/EDAV new/test_50/DEBOUNCING.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DEBOUNCING " "Info: Found entity 1: DEBOUNCING" {  } { { "DEBOUNCING.vhd" "" { Text "G:/EDAV new/test_50/DEBOUNCING.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "keys_test.vhd 2 1 " "Warning: Using design file keys_test.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 keys_test-a " "Info: Found design unit 1: keys_test-a" {  } { { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 keys_test " "Info: Found entity 1: keys_test" {  } { { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "keys_test " "Info: Elaborating entity \"keys_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "CLK_KEYBOARD keys_test.vhd(31) " "Info (10035): Verilog HDL or VHDL information at keys_test.vhd(31): object \"CLK_KEYBOARD\" declared but not used" {  } { { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 31 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "S keys_test.vhd(47) " "Info (10035): Verilog HDL or VHDL information at keys_test.vhd(47): object \"S\" declared but not used" {  } { { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 47 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DEBOUNCING DEBOUNCING:\\debounuing:U1 " "Info: Elaborating entity \"DEBOUNCING\" for hierarchy \"DEBOUNCING:\\debounuing:U1\"" {  } { { "keys_test.vhd" "\\debounuing:U1" { Text "G:/EDAV new/test_50/keys_test.vhd" 69 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d0 DEBOUNCING.vhd(68) " "Warning (10492): VHDL Process Statement warning at DEBOUNCING.vhd(68): signal \"d0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DEBOUNCING.vhd" "" { Text "G:/EDAV new/test_50/DEBOUNCING.vhd" 68 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "d1 DEBOUNCING.vhd(68) " "Warning (10492): VHDL Process Statement warning at DEBOUNCING.vhd(68): signal \"d1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DEBOUNCING.vhd" "" { Text "G:/EDAV new/test_50/DEBOUNCING.vhd" 68 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "DEBOUNCING:\\debounuing:U1\|\\free_counter:QQ\[4\] DEBOUNCING:\\debounuing:U4\|\\free_counter:QQ\[4\] " "Info: Duplicate register \"DEBOUNCING:\\debounuing:U1\|\\free_counter:QQ\[4\]\" merged to single register \"DEBOUNCING:\\debounuing:U4\|\\free_counter:QQ\[4\]\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DEBOUNCING:\\debounuing:U2\|\\free_counter:QQ\[4\] DEBOUNCING:\\debounuing:U4\|\\free_counter:QQ\[4\] " "Info: Duplicate register \"DEBOUNCING:\\debounuing:U2\|\\free_counter:QQ\[4\]\" merged to single register \"DEBOUNCING:\\debounuing:U4\|\\free_counter:QQ\[4\]\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DEBOUNCING:\\debounuing:U3\|\\free_counter:QQ\[4\] DEBOUNCING:\\debounuing:U4\|\\free_counter:QQ\[4\] " "Info: Duplicate register \"DEBOUNCING:\\debounuing:U3\|\\free_counter:QQ\[4\]\" merged to single register \"DEBOUNCING:\\debounuing:U4\|\\free_counter:QQ\[4\]\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DEBOUNCING:\\debounuing:U1\|\\free_counter:d0 DEBOUNCING:\\debounuing:U4\|\\free_counter:d0 " "Info: Duplicate register \"DEBOUNCING:\\debounuing:U1\|\\free_counter:d0\" merged to single register \"DEBOUNCING:\\debounuing:U4\|\\free_counter:d0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DEBOUNCING:\\debounuing:U2\|\\free_counter:d0 DEBOUNCING:\\debounuing:U4\|\\free_counter:d0 " "Info: Duplicate register \"DEBOUNCING:\\debounuing:U2\|\\free_counter:d0\" merged to single register \"DEBOUNCING:\\debounuing:U4\|\\free_counter:d0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DEBOUNCING:\\debounuing:U3\|\\free_counter:d0 DEBOUNCING:\\debounuing:U4\|\\free_counter:d0 " "Info: Duplicate register \"DEBOUNCING:\\debounuing:U3\|\\free_counter:d0\" merged to single register \"DEBOUNCING:\\debounuing:U4\|\\free_counter:d0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "BCD_CODE\[5\] GND " "Warning: Pin \"BCD_CODE\[5\]\" stuck at GND" {  } { { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "BCD_CODE\[6\] GND " "Warning: Pin \"BCD_CODE\[6\]\" stuck at GND" {  } { { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "BCD_CODE\[7\] GND " "Warning: Pin \"BCD_CODE\[7\]\" stuck at GND" {  } { { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "100 " "Info: Implemented 100 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "76 " "Info: Implemented 76 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 28 15:16:34 2006 " "Info: Processing ended: Wed Jun 28 15:16:34 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}