keys_test.tan.qmsg

4*8矩阵键盘的驱动程序。QuartusII5.0编译通过！

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "\\counter:Q\[0\] " "Info: Detected ripple clock \"\\counter:Q\[0\]\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "\\counter:Q\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "\\counter:Q\[2\] " "Info: Detected ripple clock \"\\counter:Q\[2\]\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "\\counter:Q\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_4M register DEBOUNCING:\\debounuing:U1\|dly register \\key_decoder:ZOUT\[0\] 185.01 MHz 5.405 ns Internal " "Info: Clock \"CLK_4M\" has Internal fmax of 185.01 MHz between source register \"DEBOUNCING:\\debounuing:U1\|dly\" and destination register \"\\key_decoder:ZOUT\[0\]\" (period= 5.405 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.423 ns + Longest register register " "Info: + Longest register to register delay is 5.423 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DEBOUNCING:\\debounuing:U1\|dly 1 REG LC_X25_Y20_N1 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y20_N1; Fanout = 12; REG Node = 'DEBOUNCING:\\debounuing:U1\|dly'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "" { DEBOUNCING:\debounuing:U1|dly } "NODE_NAME" } "" } } { "DEBOUNCING.vhd" "" { Text "G:/EDAV new/test_50/DEBOUNCING.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.241 ns) + CELL(0.590 ns) 1.831 ns Mux~2083 2 COMB LC_X24_Y20_N7 3 " "Info: 2: + IC(1.241 ns) + CELL(0.590 ns) = 1.831 ns; Loc. = LC_X24_Y20_N7; Fanout = 3; COMB Node = 'Mux~2083'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "1.831 ns" { DEBOUNCING:\debounuing:U1|dly Mux~2083 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.292 ns) 2.903 ns Mux~2084 3 COMB LC_X23_Y20_N2 1 " "Info: 3: + IC(0.780 ns) + CELL(0.292 ns) = 2.903 ns; Loc. = LC_X23_Y20_N2; Fanout = 1; COMB Node = 'Mux~2084'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "1.072 ns" { Mux~2083 Mux~2084 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.913 ns) + CELL(0.607 ns) 5.423 ns \\key_decoder:ZOUT\[0\] 4 REG LC_X16_Y17_N8 2 " "Info: 4: + IC(1.913 ns) + CELL(0.607 ns) = 5.423 ns; Loc. = LC_X16_Y17_N8; Fanout = 2; REG Node = '\\key_decoder:ZOUT\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "2.520 ns" { Mux~2084 \key_decoder:ZOUT[0] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.489 ns ( 27.46 % ) " "Info: Total cell delay = 1.489 ns ( 27.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.934 ns ( 72.54 % ) " "Info: Total interconnect delay = 3.934 ns ( 72.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "5.423 ns" { DEBOUNCING:\debounuing:U1|dly Mux~2083 Mux~2084 \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.423 ns" { DEBOUNCING:\debounuing:U1|dly Mux~2083 Mux~2084 \key_decoder:ZOUT[0] } { 0.000ns 1.241ns 0.780ns 1.913ns } { 0.000ns 0.590ns 0.292ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.279 ns - Smallest " "Info: - Smallest clock skew is 0.279 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M destination 9.268 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_4M\" to destination register is 9.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_4M 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.935 ns) 3.469 ns \\counter:Q\[2\] 2 REG LC_X16_Y17_N3 8 " "Info: 2: + IC(1.065 ns) + CELL(0.935 ns) = 3.469 ns; Loc. = LC_X16_Y17_N3; Fanout = 8; REG Node = '\\counter:Q\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "2.000 ns" { CLK_4M \counter:Q[2] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.088 ns) + CELL(0.711 ns) 9.268 ns \\key_decoder:ZOUT\[0\] 3 REG LC_X16_Y17_N8 2 " "Info: 3: + IC(5.088 ns) + CELL(0.711 ns) = 9.268 ns; Loc. = LC_X16_Y17_N8; Fanout = 2; REG Node = '\\key_decoder:ZOUT\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "5.799 ns" { \counter:Q[2] \key_decoder:ZOUT[0] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 33.61 % ) " "Info: Total cell delay = 3.115 ns ( 33.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.153 ns ( 66.39 % ) " "Info: Total interconnect delay = 6.153 ns ( 66.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "9.268 ns" { CLK_4M \counter:Q[2] \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.268 ns" { CLK_4M CLK_4M~out0 \counter:Q[2] \key_decoder:ZOUT[0] } { 0.000ns 0.000ns 1.065ns 5.088ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M source 8.989 ns - Longest register " "Info: - Longest clock path from clock \"CLK_4M\" to source register is 8.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_4M 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.935 ns) 3.469 ns \\counter:Q\[0\] 2 REG LC_X16_Y17_N1 29 " "Info: 2: + IC(1.065 ns) + CELL(0.935 ns) = 3.469 ns; Loc. = LC_X16_Y17_N1; Fanout = 29; REG Node = '\\counter:Q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "2.000 ns" { CLK_4M \counter:Q[0] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.809 ns) + CELL(0.711 ns) 8.989 ns DEBOUNCING:\\debounuing:U1\|dly 3 REG LC_X25_Y20_N1 12 " "Info: 3: + IC(4.809 ns) + CELL(0.711 ns) = 8.989 ns; Loc. = LC_X25_Y20_N1; Fanout = 12; REG Node = 'DEBOUNCING:\\debounuing:U1\|dly'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "5.520 ns" { \counter:Q[0] DEBOUNCING:\debounuing:U1|dly } "NODE_NAME" } "" } } { "DEBOUNCING.vhd" "" { Text "G:/EDAV new/test_50/DEBOUNCING.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 34.65 % ) " "Info: Total cell delay = 3.115 ns ( 34.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.874 ns ( 65.35 % ) " "Info: Total interconnect delay = 5.874 ns ( 65.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "8.989 ns" { CLK_4M \counter:Q[0] DEBOUNCING:\debounuing:U1|dly } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.989 ns" { CLK_4M CLK_4M~out0 \counter:Q[0] DEBOUNCING:\debounuing:U1|dly } { 0.000ns 0.000ns 1.065ns 4.809ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "9.268 ns" { CLK_4M \counter:Q[2] \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.268 ns" { CLK_4M CLK_4M~out0 \counter:Q[2] \key_decoder:ZOUT[0] } { 0.000ns 0.000ns 1.065ns 5.088ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "8.989 ns" { CLK_4M \counter:Q[0] DEBOUNCING:\debounuing:U1|dly } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.989 ns" { CLK_4M CLK_4M~out0 \counter:Q[0] DEBOUNCING:\debounuing:U1|dly } { 0.000ns 0.000ns 1.065ns 4.809ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DEBOUNCING.vhd" "" { Text "G:/EDAV new/test_50/DEBOUNCING.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "5.423 ns" { DEBOUNCING:\debounuing:U1|dly Mux~2083 Mux~2084 \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.423 ns" { DEBOUNCING:\debounuing:U1|dly Mux~2083 Mux~2084 \key_decoder:ZOUT[0] } { 0.000ns 1.241ns 0.780ns 1.913ns } { 0.000ns 0.590ns 0.292ns 0.607ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "9.268 ns" { CLK_4M \counter:Q[2] \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.268 ns" { CLK_4M CLK_4M~out0 \counter:Q[2] \key_decoder:ZOUT[0] } { 0.000ns 0.000ns 1.065ns 5.088ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "8.989 ns" { CLK_4M \counter:Q[0] DEBOUNCING:\debounuing:U1|dly } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.989 ns" { CLK_4M CLK_4M~out0 \counter:Q[0] DEBOUNCING:\debounuing:U1|dly } { 0.000ns 0.000ns 1.065ns 4.809ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK_4M 13 " "Warning: Circuit may not operate. Detected 13 non-operational path(s) clocked by clock \"CLK_4M\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "\\counter:Q\[4\] \\key_decoder:ZOUT\[0\] CLK_4M 3.113 ns " "Info: Found hold time violation between source  pin or register \"\\counter:Q\[4\]\" and destination pin or register \"\\key_decoder:ZOUT\[0\]\" for clock \"CLK_4M\" (Hold time is 3.113 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.023 ns + Largest " "Info: + Largest clock skew is 6.023 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M destination 9.268 ns + Longest register " "Info: + Longest clock path from clock \"CLK_4M\" to destination register is 9.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_4M 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.935 ns) 3.469 ns \\counter:Q\[2\] 2 REG LC_X16_Y17_N3 8 " "Info: 2: + IC(1.065 ns) + CELL(0.935 ns) = 3.469 ns; Loc. = LC_X16_Y17_N3; Fanout = 8; REG Node = '\\counter:Q\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "2.000 ns" { CLK_4M \counter:Q[2] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.088 ns) + CELL(0.711 ns) 9.268 ns \\key_decoder:ZOUT\[0\] 3 REG LC_X16_Y17_N8 2 " "Info: 3: + IC(5.088 ns) + CELL(0.711 ns) = 9.268 ns; Loc. = LC_X16_Y17_N8; Fanout = 2; REG Node = '\\key_decoder:ZOUT\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "5.799 ns" { \counter:Q[2] \key_decoder:ZOUT[0] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 33.61 % ) " "Info: Total cell delay = 3.115 ns ( 33.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.153 ns ( 66.39 % ) " "Info: Total interconnect delay = 6.153 ns ( 66.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "9.268 ns" { CLK_4M \counter:Q[2] \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.268 ns" { CLK_4M CLK_4M~out0 \counter:Q[2] \key_decoder:ZOUT[0] } { 0.000ns 0.000ns 1.065ns 5.088ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_4M source 3.245 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_4M\" to source register is 3.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_4M 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'CLK_4M'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "" { CLK_4M } "NODE_NAME" } "" } } { "keys_test.vhd" "" { Text "G:/EDAV new/test_50/keys_test.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.711 ns) 3.245 ns \\counter:Q\[4\] 2 REG LC_X16_Y17_N5 13 " "Info: 2: + IC(1.065 ns) + CELL(0.711 ns) = 3.245 ns; Loc. = LC_X16_Y17_N5; Fanout = 13; REG Node = '\\counter:Q\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "1.776 ns" { CLK_4M \counter:Q[4] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.18 % ) " "Info: Total cell delay = 2.180 ns ( 67.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 32.82 % ) " "Info: Total interconnect delay = 1.065 ns ( 32.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "3.245 ns" { CLK_4M \counter:Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK_4M CLK_4M~out0 \counter:Q[4] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "9.268 ns" { CLK_4M \counter:Q[2] \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.268 ns" { CLK_4M CLK_4M~out0 \counter:Q[2] \key_decoder:ZOUT[0] } { 0.000ns 0.000ns 1.065ns 5.088ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "3.245 ns" { CLK_4M \counter:Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK_4M CLK_4M~out0 \counter:Q[4] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.701 ns - Shortest register register " "Info: - Shortest register to register delay is 2.701 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\counter:Q\[4\] 1 REG LC_X16_Y17_N5 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y17_N5; Fanout = 13; REG Node = '\\counter:Q\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "" { \counter:Q[4] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.547 ns) + CELL(0.114 ns) 0.661 ns Mux~2085 2 COMB LC_X16_Y17_N0 2 " "Info: 2: + IC(0.547 ns) + CELL(0.114 ns) = 0.661 ns; Loc. = LC_X16_Y17_N0; Fanout = 2; COMB Node = 'Mux~2085'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "0.661 ns" { \counter:Q[4] Mux~2085 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.420 ns) + CELL(0.442 ns) 1.523 ns Mux~2087 3 COMB LC_X16_Y17_N9 1 " "Info: 3: + IC(0.420 ns) + CELL(0.442 ns) = 1.523 ns; Loc. = LC_X16_Y17_N9; Fanout = 1; COMB Node = 'Mux~2087'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "0.862 ns" { Mux~2085 Mux~2087 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.738 ns) 2.701 ns \\key_decoder:ZOUT\[0\] 4 REG LC_X16_Y17_N8 2 " "Info: 4: + IC(0.440 ns) + CELL(0.738 ns) = 2.701 ns; Loc. = LC_X16_Y17_N8; Fanout = 2; REG Node = '\\key_decoder:ZOUT\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "1.178 ns" { Mux~2087 \key_decoder:ZOUT[0] } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.294 ns ( 47.91 % ) " "Info: Total cell delay = 1.294 ns ( 47.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.407 ns ( 52.09 % ) " "Info: Total interconnect delay = 1.407 ns ( 52.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "2.701 ns" { \counter:Q[4] Mux~2085 Mux~2087 \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.701 ns" { \counter:Q[4] Mux~2085 Mux~2087 \key_decoder:ZOUT[0] } { 0.000ns 0.547ns 0.420ns 0.440ns } { 0.000ns 0.114ns 0.442ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "9.268 ns" { CLK_4M \counter:Q[2] \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "9.268 ns" { CLK_4M CLK_4M~out0 \counter:Q[2] \key_decoder:ZOUT[0] } { 0.000ns 0.000ns 1.065ns 5.088ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "3.245 ns" { CLK_4M \counter:Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.245 ns" { CLK_4M CLK_4M~out0 \counter:Q[4] } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "keys_test" "UNKNOWN" "V1" "G:/EDAV new/test_50/db/keys_test.quartus_db" { Floorplan "G:/EDAV new/test_50/" "" "2.701 ns" { \counter:Q[4] Mux~2085 Mux~2087 \key_decoder:ZOUT[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.701 ns" { \counter:Q[4] Mux~2085 Mux~2087 \key_decoder:ZOUT[0] } { 0.000ns 0.547ns 0.420ns 0.440ns } { 0.000ns 0.114ns 0.442ns 0.738ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}