debouncing.vhd

来自「4*8矩阵键盘的驱动程序。QuartusII5.0编译通过！」· VHDL 代码 · 共 74 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY DEBOUNCING IS
	PORT(
		clk, key:IN STD_LOGIC ;
		clr: IN	STD_LOGIC;
		dly_out, dif_out: OUT	STD_LOGIC);
END DEBOUNCING;
ARCHITECTURE a OF DEBOUNCING IS
	SIGNAL sample,dly,diff: STD_LOGIC;
BEGIN
free_counter:block
	signal QQ:std_logic_vector(4 downto 0);
	signal d0:std_logic;
begin
	process (CLR,clk)
	begin
	if clr='0' then
		d0<='0';
		QQ<=(OTHERS=>'0');
	ELSif clk'event and clk='1' then
		d0<=QQ(4);
		QQ<=QQ+1;
	end if;
	end process;
sample<=not(QQ(4) and (not d0));
end block free_counter;
debunce:block
	signal d0,d1,s,r:std_logic;
begin
	process(clk,clr)
	begin
	if clr='0' then
		dly<='0';
	elsif rising_edge(clk) then
		if sample='1' then
			d1<=d0;
			d0<=key;
			s<=d0 and d1;
			r<=not d0 and not d1;
			if s<='0' and r<='0' then
				dly<=dly;
			elsif s<='0' and r<='1' then
				dly<='0';
			elsif s<='1' and r<='0' then
				dly<='1';
			else
				dly<='0';
			end if;
		end if;
	end if;
	end process;
dly_out<=dly;
end block debunce;
differential:block
	signal d1,d0:std_logic;
begin
	process(clk,clr)
	begin
	if clr='0' then
		d0<='0';
		d1<='0';
	elsif rising_edge(clk) then
		d1<=d0;
		d0<=dly;
	end if;
		diff<=d0 and not d1;
	end process;
	dif_out<=diff;
end block differential;
END a;