sci.map.qmsg

VHDL写的SCI接口。quartusII6.0的工程！

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 28 12:13:27 2006 " "Info: Processing started: Wed Jun 28 12:13:27 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sci -c sci " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sci -c sci" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/EDAV new/test44/sci.vhd " "Warning: Can't analyze file -- file G:/EDAV new/test44/sci.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sci.vhd 2 1 " "Warning: Using design file sci.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sci-rtl " "Info: Found design unit 1: sci-rtl" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sci " "Info: Found entity 1: sci" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sci " "Info: Elaborating entity \"sci\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cs sci.vhd(71) " "Warning (10492): VHDL Process Statement warning at sci.vhd(71): signal \"cs\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 71 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "do_latch sci.vhd(85) " "Warning (10492): VHDL Process Statement warning at sci.vhd(85): signal \"do_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 85 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(151) " "Warning (10492): VHDL Process Statement warning at sci.vhd(151): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 151 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(152) " "Warning (10492): VHDL Process Statement warning at sci.vhd(152): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 152 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(153) " "Warning (10492): VHDL Process Statement warning at sci.vhd(153): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 153 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(154) " "Warning (10492): VHDL Process Statement warning at sci.vhd(154): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 154 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(155) " "Warning (10492): VHDL Process Statement warning at sci.vhd(155): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 155 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(156) " "Warning (10492): VHDL Process Statement warning at sci.vhd(156): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 156 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(157) " "Warning (10492): VHDL Process Statement warning at sci.vhd(157): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 157 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din_latch sci.vhd(158) " "Warning (10492): VHDL Process Statement warning at sci.vhd(158): signal \"din_latch\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 158 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "tdEMPTY_s txdF " "Info: Duplicate register \"tdEMPTY_s\" merged to single register \"txdF\"" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 71 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "75 " "Info: Implemented 75 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "58 " "Info: Implemented 58 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 28 12:13:34 2006 " "Info: Processing ended: Wed Jun 28 12:13:34 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}