sci.fit.qmsg

VHDL写的SCI接口。quartusII6.0的工程！

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.449 ns register register " "Info: Estimated most critical path is register to register delay of 3.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxdF 1 REG LAB_X1_Y23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y23; Fanout = 3; REG Node = 'rxdF'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { rxdF } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.590 ns) 1.445 ns do_latch\[0\]~7 2 COMB LAB_X2_Y24 8 " "Info: 2: + IC(0.855 ns) + CELL(0.590 ns) = 1.445 ns; Loc. = LAB_X2_Y24; Fanout = 8; COMB Node = 'do_latch\[0\]~7'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "1.445 ns" { rxdF do_latch[0]~7 } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.137 ns) + CELL(0.867 ns) 3.449 ns do_latch\[4\] 3 REG LAB_X1_Y25 1 " "Info: 3: + IC(1.137 ns) + CELL(0.867 ns) = 3.449 ns; Loc. = LAB_X1_Y25; Fanout = 1; REG Node = 'do_latch\[4\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "2.004 ns" { do_latch[0]~7 do_latch[4] } "NODE_NAME" } "" } } { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 42.24 % ) " "Info: Total cell delay = 1.457 ns ( 42.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.992 ns ( 57.76 % ) " "Info: Total interconnect delay = 1.992 ns ( 57.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "3.449 ns" { rxdF do_latch[0]~7 do_latch[4] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "process0~0 " "Info: Following pins have the same output enable: process0~0" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[0\] LVTTL " "Info: Type bidirectional pin data\[0\] uses the LVTTL I/O standard" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { data[0] } "NODE_NAME" } "" } } { "G:/EDAV new/test_53/sci.fld" "" { Floorplan "G:/EDAV new/test_53/sci.fld" "" "" { data[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[1\] LVTTL " "Info: Type bidirectional pin data\[1\] uses the LVTTL I/O standard" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { data[1] } "NODE_NAME" } "" } } { "G:/EDAV new/test_53/sci.fld" "" { Floorplan "G:/EDAV new/test_53/sci.fld" "" "" { data[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[2\] LVTTL " "Info: Type bidirectional pin data\[2\] uses the LVTTL I/O standard" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { data[2] } "NODE_NAME" } "" } } { "G:/EDAV new/test_53/sci.fld" "" { Floorplan "G:/EDAV new/test_53/sci.fld" "" "" { data[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[3\] LVTTL " "Info: Type bidirectional pin data\[3\] uses the LVTTL I/O standard" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { data[3] } "NODE_NAME" } "" } } { "G:/EDAV new/test_53/sci.fld" "" { Floorplan "G:/EDAV new/test_53/sci.fld" "" "" { data[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[4\] LVTTL " "Info: Type bidirectional pin data\[4\] uses the LVTTL I/O standard" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { data[4] } "NODE_NAME" } "" } } { "G:/EDAV new/test_53/sci.fld" "" { Floorplan "G:/EDAV new/test_53/sci.fld" "" "" { data[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[5\] LVTTL " "Info: Type bidirectional pin data\[5\] uses the LVTTL I/O standard" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { data[5] } "NODE_NAME" } "" } } { "G:/EDAV new/test_53/sci.fld" "" { Floorplan "G:/EDAV new/test_53/sci.fld" "" "" { data[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[6\] LVTTL " "Info: Type bidirectional pin data\[6\] uses the LVTTL I/O standard" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { data[6] } "NODE_NAME" } "" } } { "G:/EDAV new/test_53/sci.fld" "" { Floorplan "G:/EDAV new/test_53/sci.fld" "" "" { data[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data\[7\] LVTTL " "Info: Type bidirectional pin data\[7\] uses the LVTTL I/O standard" {  } { { "sci.vhd" "" { Text "G:/EDAV new/test_53/sci.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sci" "UNKNOWN" "V1" "G:/EDAV new/test_53/db/sci.quartus_db" { Floorplan "G:/EDAV new/test_53/" "" "" { data[7] } "NODE_NAME" } "" } } { "G:/EDAV new/test_53/sci.fld" "" { Floorplan "G:/EDAV new/test_53/sci.fld" "" "" { data[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 28 12:13:53 2006 " "Info: Processing ended: Wed Jun 28 12:13:53 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}